30-nm inverted in 0.53Ga 0.47As MOSHEMTs on Si substrate grown by MOCVD with regrown source/drain

IEEE Electron Device Letters

Volumn 33, Issue 10, 2012, Pages 1384-1386

  Zhou, Xiuju ^a   Li, Qiang ^a   Tang, Chak Wah ^a   Lau, Kei May ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

30 nm channel length; Effective mobility; InAlAs InGaAs MOSHEMT; selective regrowth

Indexed keywords

CHANNEL LENGTH; EFFECTIVE MOBILITIES; GATE RECESS ETCHING; HIGH QUALITY; MAXIMUM DRAIN CURRENT; METAMORPHIC GROWTH; MOSHEMT; ON-RESISTANCE; PARASITIC RESISTANCES; PEAK TRANSCONDUCTANCE; SELECTIVE REGROWTH; SI SUBSTRATES; SOURCE/DRAIN REGIONS; SUBTHRESHOLD SLOPE;

ELECTRON DEVICES; ELECTRONICS ENGINEERING;

SILICON;

EID: 84866899940     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2210383     Document Type: Article

References (16)

1. J. A. del Alamo, D.-H. Kim, T.-W. Kim, D. Jin, and D. A. Antoniadis, "III-V CMOS: What have we learned from HEMTs?" in Proc. 23rd Int. Conf. IPRM, 2011, pp. 1-4.
2. Y. Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. D. Ye, "High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/?m: New HBr pretreatment and channel engineering," in IEDM Tech. Dig., 2009, pp. 1-4.
3. U. Singisetti, M. A. Wistey, G. J. Burek, A. K. Baraskar, B. J. Thibeault, A. C. Gossard, M. J. W. Rodwell, B. Shin, E. J. Kim, P. C. McIntyre, B. Yu, Y. Yuan, D. Wang, Y. Taur, P. Asbeck, and Y.-J. Lee, "In0.53Ga0.47As channel MOSFETs with self-aligned InAs source/drain formed by MEE regrowth," IEEE Electron Device Lett., vol. 30, no. 11, pp. 1128-1130, Nov. 2009.
4. R. Terao, T. Kanazawa, S. Ikeda, Y. Yonai, A. Kato, and Y. Miyamoto, "InP/InGaAs composite metal-oxide-semiconductor field-effect transistors with regrown source and Al2O3 gate dielectric exhibiting maximum drain current exceeding 1.3 mA/?m," Appl. Phys. Exp., vol. 4, no. 5, pp. 054201-1-054201-3, May 2011.
5. M. Egard, L. Ohlsson, B. M. Borg, F. Lenrick, R. Wallenberg, L.-E.Wernersson, and E. Lind, "High transconductance self-aligned gatelast surface channel In0.53Ga0.47As MOSFET," in IEDM Tech. Dig., 2011, pp. 13.2.1-13.2.4.
6. Y. Yonai, T. Kanazawa, D. Ikeda, and Y. Miyamoto, "High drain current ( > 2 A/mm) InGaAs channel MOSFET at VD = 0.5 V with shrinkage of channel length by InP anisotropic etching," in IEDM Tech. Dig., 2011, pp. 13.3.1-13.3.4.
7. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, "Advanced high-K gate dielectric for high- performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications," in IEDM Tech. Dig., 2009, pp. 1-4.
8. M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit, and R. Chau, "Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin ( < 2 um) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications," in IEDM Tech. Dig., 2007, pp. 625-628.
9. K. M. Lau, C. W. Tang, H. O. Li, and Z. Y. Zhong, "AlInAs/GaInAs mHEMTs on silicon substrates grown by MOCVD," in IEDM Tech. Dig., 2008, pp. 1-4.
10. N. Mukherjee, J. Boardman, B. Chu-Kung, G. Dewey, A. Eisenbach, J. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, M. Radosavljevic, T. Stewart, H. W. Then, P. Tolchinsky, and R. Chau, "MOVPE III-V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications," in IEDM Tech. Dig., 2011, pp. 35.1.1-35.1.4.
11. M. Li, H. Li, C. W. Tang, and K. M. Lau, "Fabrication of 100-nm metamorphic AlInAs/GaInAs HEMTs on Si substrates by MOCVD," IEEE Electron Device Lett., vol. 33, no. 4, pp. 498-500, Apr. 2012.
12. T.-W. Kim, D.-H. Kim, and J. A. del Alamo, "30 nm In0.7Ga0.3As inverted-type HEMTs with reduced gate leakage current for logic applications," in IEDM Tech. Dig., 2009, pp. 1-4.
13. F. Xue, A. Jiang, H. Zhao, Y.-T. Chen, Y.Wang, F. Zhou, and J. Lee, "Sub- 50-nm In0.7Ga0.3As MOSFETs with various barrier layer materials," IEEE Electron Device Lett., vol. 33, no. 1, pp. 32-34, Jan. 2012.
14. J. A. del Alamo, "Nanometer-scale electronics with III-V compound semiconductors," Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011.
15. S. J. Bentley, M. Holland, X. Li, G. W. Paterson, H. Zhou, O. Ignatova, D. Macintyre, S. Thoms, A. Asenov, B. Shin, J. Ahn, P. C. McIntyre, and I. G. Thayne, "Electron mobility in surface- and buried-channel flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 gate dielectric," IEEE Electron Device Lett., vol. 32, no. 4, pp. 494-496, Apr. 2011.
16. H. Zhao, Y.-T. Chen, J. H. Yum, Y. Wang, N. Goel, and J. C. Lee, "High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility > 4400 cm2/V. s using InP barrier layer," Appl. Phys. Lett., vol. 94, no. 19, pp. 193502-1-193502-3, May 2009.