Multi-optimization power management for chip multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2008, Pages 177-186

  Meng, Ke ^a   Joseph, Russ ^a   Dick, Robert P ^a   Shang, Li ^b  

^a NORTHWESTERN UNIVERSITY   (United States)

^b UNIVERSITY OF COLORADO   (United States)

Author keywords

Cache Resizing; Chip Multi Processor; Dynamic Power Management; Voltage Frequency Scaling

Indexed keywords

ANALYTIC MODELING; CACHE RESIZING; CHIP MULTI-PROCESSOR; CONFIGURABLE PROCESSOR CORES; DESIGN CONSTRAINTS; DYNAMIC POWER MANAGEMENT; MULTI CORES; MULTI OPTIMIZATIONS; NON ADDITIVES; OPTIMIZATION STRATEGIES; PERFORMANCE LOSS; POTENTIAL BENEFITS; POWER BUDGETS; POWER MANAGEMENTS; POWER OPTIMIZATIONS; POWER SAVINGS; PROCESSOR POWER CONSUMPTION; RISK EVALUATIONS; RUN-TIME; RUN-TIME ADAPTATIONS; TRIAL-AND-ERROR APPROACHES; TRIAL-AND-ERROR METHODS; VARIABLE PERFORMANCE; VOLTAGE/FREQUENCY SCALING;

DECODING; ELECTRIC POWER MEASUREMENT; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PARALLEL ARCHITECTURES; SYSTEMS ANALYSIS;

CONSTRAINED OPTIMIZATION;

EID: 63549102138     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454141     Document Type: Conference Paper

References (33)

1. D. H. Albonesi. Selective cache ways: On-demand cache resource allocation. In International Symposium on Microarchitecture, Nov., 1999.
2. R. D. Armstrong, D. S. Kung, P. Sinha, and A. A. Zoltners. A computational study of a multiple-choice knapsack algorithm. ACM Transactions on Mathematical Software, 9(2), June 1983.
3. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-oriented full-system simulation using M5. In Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003.
4. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA-7), January 2001.
5. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA-27), June 2000.
6. A. Buyuktosunoglu, T. Karkhanis, D. H. Albonesi, and P. Bose. Energy efficient co-adaptive instruction fetch and issue. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA-30), May 2003.
7. A. Dhodapkar. Autonomic Management of Adaptive Microarchitectures. PhD thesis, University of Wisconsin-Madison, 2004.
8. A. Dhodapkar and J. E. Smith. Managing multi-configuration hardware via dynamic working set analysis. In Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002.
9. A. Dhodapkar and J. E. Smith. Tuning recongurable microarchitectures for power efficiency. In The 11th Recongurable Architectures Workshop (RAW 2004), held in conjunction with the 18th International Parallel and Distributed Processing Symposium, April 2004.
10. A. S. Dhodapkar and J. E. Smith. Comparing program phase detection techniques. In MICRO-36, December 2003.
11. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate CPI components. In ASPLOS'00, December 2000.
12. D. Folegnani and A. Gonzalez. Reducing power consumption of the issue logic. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA-28), July 2001.
13. R. Gonzalez and M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277-84, 1996.
14. L. Gwennap. Digital 21264 sets new standard. Microprocessor Report, pages 11-16, Oct. 28, 1996.
15. M. Huang, J. Renau, S.-M. Yoo, and J. Torrellas. A framework for dynamic energy efficiency and temperature management. In MICRO-33, December 2000.
16. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the 36th International Symposium on Microarchitecture (MICRO-39), December 2006.
17. C. Isci and M. Martonosi. Runtime power monitoring in high-end processors: Methodology and empirical data. In Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36), December 2003.
18. T. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA-31, June 2004.
19. T. Karkhanis and J. E. Smith. Automated design of application-specific superscalar processors. In ISCA-33, June 2006.
20. S. Kaxiras and P. Xekalakis. 4t-Decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. In ISLPED' 04, August 2004.
21. R. Kumar, K. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36), December 2003.
22. Y. Li, K. Skadron, Z. Hu, and D. Brooks. Performance, energy, and thermal considerations for SMT and CMP architectures. In Eleventh International Conference on High Performance Computer Architectures (HPCA-11), February 2005.
23. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM Journal of Research and Development, 9(2), 1970.
24. R. McGowen, C. A. Poirier, C. Bostak, et al. Power and temperature control on a 90-nm Itanium Family processor. IEEE Journal of Solid-State Circuits, 41(1), January 2006.
25. A. Mericas. Performance monitoring on the Power5 microprocessor. In Performance Evaluation and Benchmarking, pages 247-266. CRC Press, 2006.
26. F. J. Mesa-Martinez, J. Nayfach-Battilana, and J. Renau. Power model validation through thermal measurements. In ISCA-34, June 2007.
27. M. Powell, M. Gomaa, and T. Vijaykumar. Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system. In Proceedings of the Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), October 2004.
28. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Micro-39, December 2006.
29. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. on VLSI Systems, 12:131-139, Feb. 2004.
30. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2007. http://www.itrs.net/Links/2007ITRS/Home2007.htm.
31. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct 2002.
32. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA-30), June 2003.
33. S. Tam, S. Rusu, J. Chang, S. Vora, B. Cherkauer, and D. Ayers. A 65nm 95W Dual-core multi-threaded Xeon Processor with L3 cache. In IEEE Asian Solid-State Circuits Conference, November 2006.