Ultra-low power hybrid CMOS-magnetic logic architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 59, Issue 9, 2012, Pages 2008-2016

  Das, Jayita ^a   Alam, Syed M ^b   Bhanja, Sanjukta ^a  

^a University of South Florida   (United States)

^b Everspin Technologies   (United States)

Author keywords

22 nm CMOS integration; Low power; MTJ; nanomagnetic logic; spin transfer torque; STT clock; STT write; TMR based differential read; variability tolerant

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; ELECTRIC WIRE; ENERGY EFFICIENCY; INTEGRATION; MAGNETIC COUPLINGS; MAGNETIC DEVICES; NANOMAGNETICS; TUNNEL JUNCTIONS;

CMOS INTEGRATION; DIFFERENTIAL READS; LOW POWER; NANOMAGNETIC LOGIC; SPIN TRANSFER TORQUE; STT WRITE; VARIABILITY TOLERANT;

COMPUTER CIRCUITS;

EID: 84865674933     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2012.2185311     Document Type: Article

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