An efficient tree architecture for modulo 2n + 1 multiplication

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 14, Issue 3, 1996, Pages 241-248

  Wang, Zhongde ^a,b   Jullien, G A ^a   Miller, W C ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

^b STMicroelectronics USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY CODES; EFFICIENCY; MULTIPLYING CIRCUITS; RECURSIVE FUNCTIONS; SIGNAL ENCODING; TREES (MATHEMATICS); VLSI CIRCUITS;

FERMAT NUMBER TRANSFORM;

SIGNAL PROCESSING;

EID: 0030399263     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00929618     Document Type: Review

References (16)

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