Is 3D integration the way to future dependable computing platforms?

Proceedings of the International Conference on Optimisation of Electrical and Electronic Equipment, OPTIM

Volumn , Issue , 2012, Pages 1233-1242

  Safiruddin, Saleh ^a   Borodin, Demid ^a   Lefter, Mihai ^a   Voicu, George ^a   Dan Cotofana, Sorin ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

3D integration; dependable computing; fault tolerance; reliability; through silicon vias

Indexed keywords

3-D INTEGRATION; CMOS TECHNOLOGY; DEPENDABLE COMPUTING; DESIGN SPACES; DIFFERENT PLANES; NEW DIMENSIONS; PACKAGE SIZE; PHYSICAL LIMITATIONS; SOLUTION SPACE; SYSTEM RELIABILITY; SYSTEMS LEVELS; TECHNOLOGY SCALING; THROUGH SILICON VIAS; TRANSISTOR DENSITY;

CMOS INTEGRATED CIRCUITS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATION; OPTIMIZATION; RELIABILITY;

THREE DIMENSIONAL;

EID: 84864701496     PISSN: 18420133     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OPTIM.2012.6231859     Document Type: Conference Paper

References (42)

1. "International technology roadmap for semiconductors," ITRS, Tech. Rep., 2009. [Online]. Available: http://www.itrs.net/
2. A. Avizienis, J. Laprie, B. Randell, and C. Landwehr, "Basic concepts and taxonomy of dependable and secure computing," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 1, pp. 11-33, 2004.
3. A. Avizienis, "Faulty-Tolerant computing: An overview," Computer, vol. 4, no. 1, pp. 5-8, 1971.
4. P. K. Lala, Ed., Self-checking and fault-tolerant digital design. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2001.
5. B. W. Johnson, The Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley, 1989, published: Hardcover.
6. D. P. Siewiorek and R. S. Swarz, Reliable computer systems (3rd ed.): design and evaluation. Natick, MA, USA: A. K. Peters, Ltd., 1998.
7. D. K. Pradhan, Ed., Fault-tolerant computer system design. Upper Saddle River, NJ, USA: Prentice-Hall, Inc., 1996.
8. J. v. Neumann, "Probabilistic logics and synthesis of reliable organisms from unreliable components," in Automata Studies, C. Shannon and J. McCarthy, Eds. Princeton University Press, 1956, pp. 43-98.
9. A. Avizienis, "The hundred year spacecraft," in Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, 1999, pp. 233-239.
10. D. Rennels, "Fault-Tolerant computing - concepts and examples," IEEE Transactions on Computers, vol. 100, no. 12, pp. 1116-1129, 1984.
11. L. Chen and A. Avizienis, "N-version programming: a fault-tolerance approach to reliability," in Proc 8th IEEE Int Symp on Fault Tolerant Computing FTCS8, vol. 1, 1978, pp. 3-9.
12. C. Stroud, "Reliability of majority voting based VLSI fault-tolerant circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 516-521, Dec. 1994.
13. C. Metra, M. Favalli, and B. Ricco, "Compact and low power on-line self-testing voting scheme," in In Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997, pp. 137-145.
14. J. M. Cazeaux, D. Rossi, and C. Metra, "Self-Checking voter for high speed TMR systems," J. Electron. Test., vol. 21, no. 4, pp. 377-389, Aug. 2005.
15. H. El-Razouk and Z. Abid, "A new transistor-redundant voter for defect-tolerant digital circuits," in Canadian Conference on Electrical and Computer Engineering, CCECE'06., 2006, pp. 1078-1081.
16. S. Mitra and E. McCluskey, "Word-voter: A new voter design for triple modular redundant systems," in Proceedings of the 18th IEEE VLSI Test Symposium, 2000, p. 465470.
17. J. Lala and R. Harper, "Architectural principles for safety-critical realtime applications," Proceedings of the IEEE, vol. 82, no. 1, pp. 25-40, 1994.
18. D. Reynolds and G. Metze, "Fault detection capabilities of alternating logic," IEEE Transactions on Computers, vol. 100, no. 12, pp. 1093-1098, 1978.
19. J. Shedletsky, "Error correction by alternate-data retry," IEEE Transactions on Computers, vol. 100, no. 2, pp. 106-112, 1978.
20. J. Patel and L. Fung, "Concurrent error detection in ALU's by recomputing with shifted operands," Computers, IEEE Transactions on, vol. 100, no. 7, p. 589595, 1982.
21. J. Li and E. Swartzlander Jr, "Concurrent error detection in ALUs by recomputing with rotated operands," in Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1992, p. 109116.
22. B. Johnson, J. Aylor, and H. Hana, "Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder," IEEE Journal of Solid-State Circuits, vol. 23, no. 1, pp. 208-215, 1988.
23. Y. Hsu and E. Swartzlander Jr, "Time redundant error correcting adders and multipliers," in Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1992, pp. 247-256.
24. T. Ngai, C. He, and E. Swartzlander Jr, "Enhanced concurrent error correcting arithmetic unit design using alternating logic," in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 78-83.
25. K. Huang and J. Abraham, "Algorithm-based fault tolerance for matrix operations," IEEE Transactions on Computers, vol. 100, no. 6, pp. 518-528, 1984.
26. J. Early, "Speed, power and component density in multielement highspeed logic systems," in IEEE International Solid-State Circuits Conference, Feb. 1960, pp. 78-79.
27. D. Lu, Materials for advanced packaging. Springer, 2008.
28. S. Wong, A. El-Gamal, P. Griffin, Y. Nishi, F. Pease, and J. Plummer, "Monolithic 3D integrated circuits," in International Symposium on VLSI Technology, Systems and Applications, 2007, pp. 1-4.
29. J. Lau, "Evolution and outlook of TSV and 3D IC/Si integration," in 12th Electronics Packaging Technology Conference (EPTC), 2010, pp. 560-570.
30. D. Choudhury, "3D integration technologies for emerging microsystems," in IEEE MTT-S International Microwave Symposium Digest (MTT), 2010, pp. 1-4.
31. N. Sillon, A. Astier, H. Boutry, L. Di Cioccio, D. Henry, and P. Leduc, "Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs," in IEEE International Electron Devices Meeting, 2008, pp. 1-4.
32. J. Kim, C. S. Oh, H. Lee, D. Lee, H. Hwang, S. Hwang, B. Na, J. Moon, J. Kim, H. Park, J. Ryu, K. Park, S. Kang, S. Kim, H. Kim, J. Bang, H. Cho, M. Jang, C. Han, J. Lee, K. Kyung, J. Choi, and Y. Jun, "A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-Based stacking," in IEEE International Solid-State Circuits Conference, Feb. 2011, pp. 496-498.
33. M. Santarini, "Stacked & loaded: Xilinx SSI, 28-Gbps I/O yield amazing FPGAs," Xcell Journal, no. 74, pp. 8-13, 2011.
34. J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, "Interconnect limit on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE, vol. 89, no. 3, pp. 305-324, 2001.
35. G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for Three-Dimensional ICs," IEEE Transactions on Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
36. N. Sillon, A. Astier, H. Boutry, L. Di Cioccio, D. Henry, and P. Leduc, "Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs," in IEEE International Electron Devices Meeting, 2008, pp. 1-4.
37. E. Jung, A. Ostmann, P. Ramm, J. Wolf, M. Toepper, and M. Wiemer, "Through silicon vias as enablers for 3D systems," in Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, Nice, 2008, pp. 119-122.
38. D. Borodin, B. Juurlink, S. Hamdioui, and S. Vassiliadis, "Instruction-Level fault tolerance configurability," Journal of Signal Processing Systems, vol. 57, no. 1, pp. 89-105, 2009.
39. M. Gomaa and T. Vijaykumar, "Opportunistic transient-fault detection," in 32nd International Symposium on Computer Architecture, 2005, pp. 172-183.
40. A. Parashar, S. Gurumurthi, and A. Sivasubramaniam, "A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy," ACM SIGARCH Computer Architecture News, vol. 32, no. 2, p. 376, 2004.
41. N. Madan and R. Balasubramonian, "Leveraging 3D technology for improved reliability," in Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007, p. 223235.
42. J. Xie, X. Dong, and Y. Xie, "3D memory stacking for fast Checkpointing/Restore applications," in IEEE International 3D Systems Integration Conference (3DIC), Munich, 2010, pp. 1-6.