Enhanced concurrent error correcting arithmetic unit design using alternating logic

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 78-83

  Ngai, T ^a   He, C ^a   Swartzlander, E E ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DESIGN; RELIABILITY; VLSI CIRCUITS;

ALTERNATING LOGIC; ARITHMETIC UNIT DESIGN; CONCURRENT ERROR CORRECTION; TRIPLE MODULAR REDUNDANCY;

DIGITAL ARITHMETIC;

EID: 0035197860     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Fault detection capabilities of alternating logic
2. Concurrent error detection in ALU's by recomputing with shifted operands
3. Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder
4. Achieving fault-tolerance by shifted and rotated operands in TMR non-diverse ALUs
5. Time redundant error correcting adders and multipliers
6. Logic design of fault-tolerant arithmetic units based on the data complementation strategy