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Volumn , Issue , 2008, Pages 119-122

Through silicon vias as enablers for 3D systems

Author keywords

[No Author keywords available]

Indexed keywords

3D SYSTEMS; ACTIVE CIRCUITS; COMPLEX SYSTEMS; FABRICATION PROCESS; THROUGH SILICON VIAS;

EID: 62249210280     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DTIP.2008.4752965     Document Type: Conference Paper
Times cited : (6)

References (14)
  • 1
    • 0029777955 scopus 로고    scopus 로고
    • 3D packaging technology overview and mass memory applications
    • IEEE Feb Pages
    • R. Terrill, "3D packaging technology overview and mass memory applications", Aerospace Applications Conference, 1996. Proceedings., 1996 IEEE Volume 2, Issue , 3-10 Feb 1996 Page(s):347 - 355
    • (1996) Aerospace Applications Conference, 1996. Proceedings , vol.2 , Issue.and 3-10 , pp. 347-355
    • Terrill, R.1
  • 5
    • 0036142020 scopus 로고    scopus 로고
    • P. Rombach et al,. The first low voltage, low noise differential silicon microphone, technology development and measurement results, Sensors and Actuators A, 95, Issues 2-3, 1 January 2002, Pages 196-201
    • P. Rombach et al,. "The first low voltage, low noise differential silicon microphone, technology development and measurement results", Sensors and Actuators A, Volume 95, Issues 2-3, 1 January 2002, Pages 196-201
  • 6
    • 84869258933 scopus 로고    scopus 로고
    • Ultra-thin Silicon μ-via Substrates and Integrated μ- vias for SiP Applications
    • Sept, Atlanta
    • A. Hase et al., "Ultra-thin Silicon μ-via Substrates and Integrated μ- vias for SiP Applications", Second internat. Workshop on SIP, SOP, SOC, Sept., 22-25. 2005, Atlanta
    • (2005) Second internat. Workshop on SIP, SOP, SOC , pp. 22-25
    • Hase, A.1
  • 7
    • 62249207547 scopus 로고    scopus 로고
    • L. Boettcher et al., Development of a 3D Wafer Level Re-Routing using dielectric lamination technology, Proc. SMTA 2006, Rosemont
    • L. Boettcher et al., "Development of a 3D Wafer Level Re-Routing using dielectric lamination technology", Proc. SMTA 2006, Rosemont
  • 8
    • 84869261758 scopus 로고    scopus 로고
    • Online process documentation
    • Online process documentation: http://www.virginiasemi.com/pdf/ siliconetchingandcleaning.doc
  • 10
    • 62249168418 scopus 로고    scopus 로고
    • J.L.Xaydevant, High Speed Via Drilling for 3D Interconnect Industrialization, as contribution given during 3D Integration, Technologies and Strategies, Encasit workshop, May. 11th 2006, Munich
    • J.L.Xaydevant, "High Speed Via Drilling for 3D Interconnect Industrialization", as contribution given during "3D Integration, Technologies and Strategies", Encasit workshop, May. 11th 2006, Munich
  • 11
    • 10444271693 scopus 로고    scopus 로고
    • New wafer-level-packaging technology using silicon-via-contacts for optical and other sensor applications
    • June Pages, 1
    • J. Leib et al., "New wafer-level-packaging technology using silicon-via-contacts for optical and other sensor applications", Electronic Components and Technology Conference, 2004. Proceedings. 54th, Volume 1, Issue , 1-4 June 2004 Page(s): 843 - 847 Vol.1
    • (2004) Electronic Components and Technology Conference, 2004. Proceedings. 54th , vol.1 , Issue.and 1-4 , pp. 843-847
    • Leib, J.1
  • 14
    • 34547969120 scopus 로고    scopus 로고
    • High Density Through Wafer Via Technology
    • NSTI-Nanotech, ISBN 1420061844
    • T. Bauer, "High Density Through Wafer Via Technology", NSTI-Nanotech 2007,Vol. 3, ISBN 1420061844
    • (2007) , vol.3
    • Bauer, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.