Understanding the basic advantages of bulk FinFETs for sub- and near-threshold logic circuits from device measurements

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 7, 2012, Pages 439-442

  Crupi, F ^a,b   Alioto, M ^b   Franco, J ^c,d   Magnone, P ^e   Togo, M ^c   Horiguchi, N ^c   Groeseneken, G ^c,d  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c IMEC   (Belgium)

^d UNIVERSITY OF LEUVEN   (Belgium)

^e UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Bulk FinFET; digital circuits; subthreshold CMOS; VLSI

Indexed keywords

BIAS VOLTAGE; DIGITAL CIRCUITS; DRAIN CURRENT; FINFET; FINS (HEAT EXCHANGE); LOGIC CIRCUITS; THRESHOLD LOGIC; THRESHOLD VOLTAGE; TIMING CIRCUITS; VOLTAGE SCALING;

BULK FINFET; CHANNEL LENGTH; EQUIVALENT THICKNESS; GATE VOLTAGES; NEAR THRESHOLDS; PLANAR DEVICES; SUBTHRESHOLD CMOS; VLSI;

COMPUTER CIRCUITS;

EID: 84864124969     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2200171     Document Type: Article

References (11)

1. M. Alioto, "Ultra-low power VLSI circuit design demystified and explained: A tutorial," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3-29, Jan. 2012.
2. A.Chandrakasan,D.C.Daly,D.F.Finchelstein, J.Kwong,Y. K. Ramadass, M. E. Sinangil, V. Sze, N. Verma et al., "Technologies for ultradynamic voltage scaling," Proc. IEEE, vol. 98, no. 2, pp. 191-214, Feb. 2010.
3. J. Rabaey, J. Ammer, B. Otis, F. Burghardt, Y. H. Chee, N. Pletcher, M. Sheets, and H. Qin, "Ultra-low-power design-The roadmap to disappearing electronics and ambient intelligence," IEEE Circuits Devices Mag., vol. 22, no. 4, pp. 23-29, Jul./Aug. 2006.
4. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005. (Pubitemid 40099941)
5. M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, "Leakage-delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 232-245, Feb. 2010.
6. P. Magnone, F. Crupi, M. Alioto, B. Kaczer, and B. De Jaeger, "Understanding the potential and the limits of germanium pMOSFETs for VLSI circuits from experimental measurements," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 9, pp. 1569-1582, Sep. 2011.
7. F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, "Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling," in Proc. IEEE Int. Symp. Circuits Syst., 2011, pp. 2249-2252.
8. F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, "Buried silicon-germanium pMOSFETs: Experimental analysis in VLSI circuits under aggressive voltage scaling," IEEE Trans. Very Large Scale Integr. (VLSI) Syst.. doi:DOI:10.1109/TVLSI.2011.2159870.
9. S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and implied insights on effective gate width," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993-1997, Sep. 2005. (Pubitemid 41410735)
10. M. Alioto, "Understanding DC behavior of subthreshold CMOS logic through closed-form analysis," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597-1607, Jul. 2010.
11. T. Chiarella, L.Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, and T. Hoffmann, "Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession," Solid State Electron., vol. 54, no. 9, pp. 855-860, Sep. 2010.