Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2249-2252

  Crupi, Felice ^a   Alioto, Massimo ^b,c   Franco, Jacopo ^d,e   Magnone, Paolo ^f   Kaczer, Ben ^d   Groeseneken, Guido ^d,e   Mitard, Jerome ^d   Witters, Liesbeth ^d   Hoffmann, Thomas Y ^d  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IMEC   (Belgium)

^e UNIVERSITY OF LEUVEN   (Belgium)

^f UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL DEVICE; COMPARATIVE ANALYSIS; DYNAMIC VOLTAGE SCALING; ENERGY-DELAY TRADE-OFF; EXPERIMENTAL ANALYSIS; FUTURE TECHNOLOGIES; GATE STACKS; LOW VOLTAGES; P-MOSFETS; PMOSFET; SIGE TECHNOLOGY; SILICON GERMANIUM; SYSTEM LEVELS; VLSI SYSTEM; VOLTAGE-SCALING; WAFER LEVEL;

ELECTRIC NETWORK ANALYSIS; GERMANIUM; LOGIC CIRCUITS; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON ALLOYS; SILICON WAFERS;

VLSI CIRCUITS;

EID: 79960853342     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938049     Document Type: Conference Paper

References (12)

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