메뉴 건너뛰기




Volumn , Issue , 2012, Pages 236-242

Functional composition: A new paradigm for performing logic synthesis

Author keywords

AIG rewriting; algorithms; Boolean properties; factoring; functional composition; Functional Decomposition; logic synthesis

Indexed keywords

AIG REWRITING; BOOLEAN PROPERTIES; FACTORING; FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS;

EID: 84863692837     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2012.6187500     Document Type: Conference Paper
Times cited : (14)

References (24)
  • 4
    • 0029216317 scopus 로고    scopus 로고
    • A Method for Finding Good Ashenhurst Decompositions and its Application to FPGA Synthesis
    • T.Stanion, C.Sechen; A Method for Finding Good Ashenhurst Decompositions and its Application to FPGA Synthesis. DAC95, pp.60-64.
    • DAC95 , pp. 60-64
    • Stanion, T.1    Sechen, C.2
  • 5
    • 33846545005 scopus 로고    scopus 로고
    • DAGaware AIG rewriting a fresh look at combinational logic synthesis
    • A.Mishchenko, S.Chatterjee, and R.Brayton. DAGaware AIG rewriting a fresh look at combinational logic synthesis. DAC '06, pp.532-535.
    • DAC '06 , pp. 532-535
    • Mishchenko, A.1    Chatterjee, S.2    Brayton, R.3
  • 7
    • 79959248098 scopus 로고    scopus 로고
    • Constructive AIG optimization considering input weights
    • T.Figueiro, R.P. Ribas, A.I. Reis. Constructive AIG optimization considering input weights; ISQED 2011, pp. 1-8
    • ISQED 2011 , pp. 1-8
    • Figueiro, T.1    Ribas, R.P.2    Reis, A.I.3
  • 8
    • 79957777320 scopus 로고    scopus 로고
    • Efficient method to compute minimum decision chains of Boolean functions
    • M.G.A. Martins, V. Callegaro, R. P. Ribas, A. I. Reis. Efficient method to compute minimum decision chains of Boolean functions. GLSVLSI 2011, pp. 419-422.
    • GLSVLSI 2011 , pp. 419-422
    • Martins, M.G.A.1    Callegaro, V.2    Ribas, R.P.3    Reis, A.I.4
  • 9
    • 34247642340 scopus 로고    scopus 로고
    • A methodology for transistor-efficient supergate design
    • D. Kagaris, T. Haniotakis. A methodology for transistor-efficient supergate design. IEEE TVLSI. Vol. 15, N. 4, pp. 488-492.
    • IEEE TVLSI , vol.15 , Issue.4 , pp. 488-492
    • Kagaris, D.1    Haniotakis, T.2
  • 11
    • 84863664448 scopus 로고    scopus 로고
    • Covering strategies for library free technology mapping
    • A.I.Reis. Covering strategies for library free technology mapping. SBCCI'99, pp. 180-183.
    • SBCCI'99 , pp. 180-183
    • Reis, A.I.1
  • 12
    • 14244252129 scopus 로고    scopus 로고
    • Advanced technology mapping for standard-cell generators
    • V.Correia, A.Reis. "Advanced technology mapping for standard-cell generators," SBCCI 2004, pp. 254- 259.
    • SBCCI 2004 , pp. 254-259
    • Correia, V.1    Reis, A.2
  • 16
    • 0033347266 scopus 로고    scopus 로고
    • Factoring logic functions using graph partitioning
    • M.C.Golumbic, A.Mintz. Factoring logic functions using graph partitioning. ICCAD '99, pp. 195-199.
    • ICCAD '99 , pp. 195-199
    • Golumbic, M.C.1    Mintz, A.2
  • 17
    • 22344435097 scopus 로고    scopus 로고
    • Factoring boolean functions using graph partitioning
    • Aug.
    • Mintz, A. and Golumbic, M. C. Factoring boolean functions using graph partitioning. Discrete Appl. Math. 149, 1-3 (Aug. 2005), 131-153.
    • (2005) Discrete Appl. Math. , vol.149 , Issue.1-3 , pp. 131-153
    • Mintz, A.1    Golumbic, M.C.2
  • 18
    • 0003647211 scopus 로고
    • Version 3.0, Technical Report 1991-IWLS-UG-Saeyang, MCNC Research Triangle Park, NC, January
    • S. Yang, Logic Synthesis and Optimization Benchmarks User Guide Version 3.0, Technical Report 1991-IWLS-UG-Saeyang, MCNC Research Triangle Park, NC, January 1991.
    • (1991) Logic Synthesis and Optimization Benchmarks User Guide
    • Yang, S.1
  • 19
    • 33745823396 scopus 로고    scopus 로고
    • FRAIGs: A Unifying Representation for Logic Synthesis and Verification
    • EECS Dept., UC Berkeley, March
    • A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton, "FRAIGs: A Unifying Representation for Logic Synthesis and Verification", ERL Technical Report, EECS Dept., UC Berkeley, March 2005.
    • (2005) ERL Technical Report
    • Mishchenko, A.1    Chatterjee, S.2    Jiang, R.3    Brayton, R.4
  • 20
    • 33847183290 scopus 로고    scopus 로고
    • Classifying n-Input Boolean Functions
    • V.P.Correia, A.I.Reis. "Classifying n-Input Boolean Functions". IBERCHIP 2001, pp. 58-66.
    • IBERCHIP 2001 , pp. 58-66
    • Correia, V.P.1    Reis, A.I.2
  • 22
    • 49749130486 scopus 로고    scopus 로고
    • High-Quality Circuit Synthesis for Modern Technologies
    • Joswiak, L., Chojnacki, A., Slusarczyk, A. High-Quality Circuit Synthesis for Modern Technologies. ISQED 2008, pp 168-173
    • ISQED 2008 , pp. 168-173
    • Joswiak, L.1    Chojnacki, A.2    Slusarczyk, A.3
  • 23
    • 57649150087 scopus 로고    scopus 로고
    • Technology Library Modelling for Information-driven Circuit Synthesis
    • L.Jozwiak, S.Bieganski. "Technology Library Modelling for Information-driven Circuit Synthesis,"EUROMICRO 2008, pp.480-489.
    • EUROMICRO 2008 , pp. 480-489
    • Jozwiak, L.1    Bieganski, S.2
  • 24
    • 0035209084 scopus 로고    scopus 로고
    • BOOM - A Heuristic Boolean Minimizer
    • Jan Hlavicka, Petr Fiser, "BOOM - a Heuristic Boolean Minimizer". ICCAD 2001, pp. 439-442.
    • ICCAD 2001 , pp. 439-442
    • Hlavicka, J.1    Fiser, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.