-
3
-
-
33751405387
-
Reducing structural bias in technology mapping
-
S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, T. Kam. "Reducing structural bias in technology mapping," ICCAD-2005, pp. 519-526.
-
ICCAD-2005
, pp. 519-526
-
-
Chatterjee, S.1
Mishchenko, A.2
Brayton, R.3
Wang, X.4
Kam, T.5
-
4
-
-
0029216317
-
A Method for Finding Good Ashenhurst Decompositions and its Application to FPGA Synthesis
-
T.Stanion, C.Sechen; A Method for Finding Good Ashenhurst Decompositions and its Application to FPGA Synthesis. DAC95, pp.60-64.
-
DAC95
, pp. 60-64
-
-
Stanion, T.1
Sechen, C.2
-
5
-
-
33846545005
-
DAGaware AIG rewriting a fresh look at combinational logic synthesis
-
A.Mishchenko, S.Chatterjee, and R.Brayton. DAGaware AIG rewriting a fresh look at combinational logic synthesis. DAC '06, pp.532-535.
-
DAC '06
, pp. 532-535
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
-
7
-
-
79959248098
-
Constructive AIG optimization considering input weights
-
T.Figueiro, R.P. Ribas, A.I. Reis. Constructive AIG optimization considering input weights; ISQED 2011, pp. 1-8
-
ISQED 2011
, pp. 1-8
-
-
Figueiro, T.1
Ribas, R.P.2
Reis, A.I.3
-
9
-
-
34247642340
-
A methodology for transistor-efficient supergate design
-
D. Kagaris, T. Haniotakis. A methodology for transistor-efficient supergate design. IEEE TVLSI. Vol. 15, N. 4, pp. 488-492.
-
IEEE TVLSI
, vol.15
, Issue.4
, pp. 488-492
-
-
Kagaris, D.1
Haniotakis, T.2
-
10
-
-
78650727962
-
Boolean factoring with multiobjective goals
-
M.G.A.Martins, L.S.Rosa Jr, A.B. Rasmussen, R.P.Ribas, A.I. Reis. "Boolean factoring with multiobjective goals," ICCD 2010, pp.229-234.
-
ICCD 2010
, pp. 229-234
-
-
Martins, M.G.A.1
Rosa Jr., L.S.2
Rasmussen, A.B.3
Ribas, R.P.4
Reis, A.I.5
-
11
-
-
84863664448
-
Covering strategies for library free technology mapping
-
A.I.Reis. Covering strategies for library free technology mapping. SBCCI'99, pp. 180-183.
-
SBCCI'99
, pp. 180-183
-
-
Reis, A.I.1
-
12
-
-
14244252129
-
Advanced technology mapping for standard-cell generators
-
V.Correia, A.Reis. "Advanced technology mapping for standard-cell generators," SBCCI 2004, pp. 254- 259.
-
SBCCI 2004
, pp. 254-259
-
-
Correia, V.1
Reis, A.2
-
13
-
-
77957900925
-
Automatic generation of digital cell libraries
-
J.D.Togni, F.R.Schneider, V.P.Correia, R.P.Ribas, A.I.Reis. "Automatic generation of digital cell libraries," SBCCI 2002, pp. 265-270.
-
SBCCI 2002
, pp. 265-270
-
-
Togni, J.D.1
Schneider, F.R.2
Correia, V.P.3
Ribas, R.P.4
Reis, A.I.5
-
14
-
-
0003934798
-
-
Tech. Rep. UCB/ERL M92/41. UC Berkeley, Berkeley
-
Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Brayton, R., and Sangiovanni-Vincentelli, A. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41. UC Berkeley, Berkeley. 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
-
-
Sentovich, E.1
Singh, K.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.8
Brayton, R.9
Sangiovanni-Vincentelli, A.10
-
16
-
-
0033347266
-
Factoring logic functions using graph partitioning
-
M.C.Golumbic, A.Mintz. Factoring logic functions using graph partitioning. ICCAD '99, pp. 195-199.
-
ICCAD '99
, pp. 195-199
-
-
Golumbic, M.C.1
Mintz, A.2
-
17
-
-
22344435097
-
Factoring boolean functions using graph partitioning
-
Aug.
-
Mintz, A. and Golumbic, M. C. Factoring boolean functions using graph partitioning. Discrete Appl. Math. 149, 1-3 (Aug. 2005), 131-153.
-
(2005)
Discrete Appl. Math.
, vol.149
, Issue.1-3
, pp. 131-153
-
-
Mintz, A.1
Golumbic, M.C.2
-
18
-
-
0003647211
-
-
Version 3.0, Technical Report 1991-IWLS-UG-Saeyang, MCNC Research Triangle Park, NC, January
-
S. Yang, Logic Synthesis and Optimization Benchmarks User Guide Version 3.0, Technical Report 1991-IWLS-UG-Saeyang, MCNC Research Triangle Park, NC, January 1991.
-
(1991)
Logic Synthesis and Optimization Benchmarks User Guide
-
-
Yang, S.1
-
19
-
-
33745823396
-
FRAIGs: A Unifying Representation for Logic Synthesis and Verification
-
EECS Dept., UC Berkeley, March
-
A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton, "FRAIGs: A Unifying Representation for Logic Synthesis and Verification", ERL Technical Report, EECS Dept., UC Berkeley, March 2005.
-
(2005)
ERL Technical Report
-
-
Mishchenko, A.1
Chatterjee, S.2
Jiang, R.3
Brayton, R.4
-
20
-
-
33847183290
-
Classifying n-Input Boolean Functions
-
V.P.Correia, A.I.Reis. "Classifying n-Input Boolean Functions". IBERCHIP 2001, pp. 58-66.
-
IBERCHIP 2001
, pp. 58-66
-
-
Correia, V.P.1
Reis, A.I.2
-
21
-
-
0029479637
-
Decompositional logic synthesis approach for look up table FPGAs
-
L. 18-22 Sep
-
F.A.M.Volf, L.Jozwiak, L.;, "Decompositional logic synthesis approach for look up table FPGAs, " IEEE International ASIC Conference and Exhibit, 1995, pp.358-361, 18-22 Sep 1995
-
(1995)
IEEE International ASIC Conference and Exhibit, 1995
, pp. 358-361
-
-
Volf, F.A.M.1
Jozwiak, L.2
-
22
-
-
49749130486
-
High-Quality Circuit Synthesis for Modern Technologies
-
Joswiak, L., Chojnacki, A., Slusarczyk, A. High-Quality Circuit Synthesis for Modern Technologies. ISQED 2008, pp 168-173
-
ISQED 2008
, pp. 168-173
-
-
Joswiak, L.1
Chojnacki, A.2
Slusarczyk, A.3
-
23
-
-
57649150087
-
Technology Library Modelling for Information-driven Circuit Synthesis
-
L.Jozwiak, S.Bieganski. "Technology Library Modelling for Information-driven Circuit Synthesis,"EUROMICRO 2008, pp.480-489.
-
EUROMICRO 2008
, pp. 480-489
-
-
Jozwiak, L.1
Bieganski, S.2
-
24
-
-
0035209084
-
BOOM - A Heuristic Boolean Minimizer
-
Jan Hlavicka, Petr Fiser, "BOOM - a Heuristic Boolean Minimizer". ICCAD 2001, pp. 439-442.
-
ICCAD 2001
, pp. 439-442
-
-
Hlavicka, J.1
Fiser, P.2
|