High-quality circuit synthesis for modern technologies

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 168-173

  Jozwiak, Lech ^a   Chojnacki, Artur ^b   Slusarczyk, Aleksander ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAD TOOLS; CIRCUIT SYNTHESIS; ELECTRONIC DESIGNS; HIGH-QUALITY; INTERNATIONAL SYMPOSIUM; LOW-POWER CIRCUITS; MICROELECTRONIC TECHNOLOGIES; MODERN TECHNOLOGIES; NANO-CMOS; NEW TECHNOLOGIES; SYNTHESIS METHODS;

COMPUTER AIDED DESIGN; ELECTRONICS ENGINEERING; NETWORKS (CIRCUITS);

TECHNOLOGY;

EID: 49749130486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479720     Document Type: Conference Paper

References (8)

1. Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 70909, http://www.eecs.berkeley. edu/∼alanmi/abc
2. J. Cong and K. Minkovich: Optimality Study of Logic Synthesis for LUT-Based FPGAs, FPGA'06, February 22-24, 2006, Monterey, California, USA, ACM, pp. 33-40.
3. L. Jóźwiak, A. Ślusarczyk: General Decomposition of Incompletely Specified Sequential Machines with Multi-State Behaviour Realisation, Journal of Systems Architecture, Vol. 50, December 2003, pp. 445-492.
4. L. Jóźwiak: Information Relationships and Measures - An Analysis Apparatus for Efficient Information System Synthesis, 23rd EUROMICRO Conference, Budapest, Hungary, September 1-4, 1997, IEEE Computer Society Press, pp. 13-23.
5. L. Jóźwiak, A. Chojnacki: Effective and efficient combinational circuit synthesis for the FPGA-based reconfigurable systems, Journal of Systems Architecture, Special Issue on Reconfigurable Computing Vol. 49 No 4-6, 2003, pp. 247-265
6. E. M. Sentovich, K. Singth, L. J., Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis, Memorandum No. UCB/ERL M92/41, Electronic Research Laboratory, University of California, Berkeley. ftp://ic.eecs.berkeley.edU/pub/Sis/Sis-paper.ps.Z
7. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, http://www.cbl.ncsu.edu/
8. The 2005 International Technology Roadmap for Semiconductors, SIA, San Jose, CA, USA, 2005, http://www.itrs.net/Links/2005ITRS/Home2005.htm