Technology library modelling for information-driven circuit synthesis

Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

Volumn , Issue , 2008, Pages 480-489

  Jóźwiak, Lech ^a   Biegański, Szymon ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAD TOOLS; CIRCUIT SYNTHESES; CMOS TECHNOLOGIES; LOW POWERS; MICROELECTRONIC TECHNOLOGIES; SYNTHESIS METHODS;

COMPUTER AIDED DESIGN; NETWORKS (CIRCUITS); SYSTEMS ANALYSIS; TECHNOLOGY;

ARCHITECTURAL DESIGN;

EID: 57649150087     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2008.13     Document Type: Conference Paper

References (8)

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2. L. Jóźwiak: General Decomposition and Its Use in Digital Circuit Synthesis, VLSI Design: An International Journal of Custom Chip Design Simulation and Testing, vol.3, No 3-4, 1995.
3. L. Jóźwiak, A. Ślusarczyk: General Decomposition of Incompletely Specified Sequential Machines with Multi-State Behaviour Realisation, Journal of Systems Architecture, Vol. 50, December 2003, pp. 445-492.
4. L. Jóźwiak: Information Relationships and Measures - An Analysis Apparatus for Efficient Information System Synthesis, 23rd EUROMICRO Conference, Budapest, Hungary, September 1-4, 1997, IEEE Computer Society Press, pp. 13-23.
5. L. Jóźwiak, S. Biegański, A. Chojnacki: Information-driven Circuit Synthesis with the Pre-characterized Gate Libraries, Journal of Systems Architecture, Elsevier Science, Amsterdam, The Netherlands, Vol. 51, No 6-7, June-July 2005, pp. 405-423.
6. E. M. Sentovich, K. Singth, L. J., Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis, Memorandum No. UCB/ERL M92/41, Electronic Research Laboratory, University of California, Berkeley. ftp://ic.eecs.berkeley.edu/pub/Sis/Sis-paper.ps.Z
7. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, http://www.cbl.ncsu.edu/
8. The 2005 International Technology Roadmap for Semiconductors, SIA, San Jose, CA, USA, 2005, http://ww.itrs.net/Links/2005ITRS/Home2005.htm