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Volumn 15, Issue 4, 2007, Pages 488-492

A methodology for transistor-efficient supergate design

Author keywords

Automatic synthesis; Switching functions; Transistors; VLSI

Indexed keywords

BOOLEAN FUNCTIONS; LOGIC DESIGN; LOGIC GATES; SWITCHING FUNCTIONS; VLSI CIRCUITS;

EID: 34247642340     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.895248     Document Type: Article
Times cited : (32)

References (15)
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    • Aug
    • G. Caruso, "Near optimal factorization of Boolean functions," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 8, pp. 1072-1078, Aug. 1991.
    • (1991) IEEE Trans. Comput.-Aided Design Integr. Circuits Syst , vol.10 , Issue.8 , pp. 1072-1078
    • Caruso, G.1
  • 8
    • 0033365094 scopus 로고    scopus 로고
    • Transistor level synthesis for static CMOS combinational circuits
    • C. R. Liu and J. A. Abraham, "Transistor level synthesis for static CMOS combinational circuits," in Proc. Great Lakes Symp. VLSI, 1999, pp. 172-175.
    • (1999) Proc. Great Lakes Symp. VLSI , pp. 172-175
    • Liu, C.R.1    Abraham, J.A.2
  • 11
    • 15044339296 scopus 로고    scopus 로고
    • Transistor-level optimization of digital designs with flex cells
    • Feb
    • R. Roy, D. Bhattacharya, and V. Boppana, "Transistor-level optimization of digital designs with flex cells," Computer, vol. 38, no. 2, pp. 53-61, Feb. 2005.
    • (2005) Computer , vol.38 , Issue.2 , pp. 53-61
    • Roy, R.1    Bhattacharya, D.2    Boppana, V.3
  • 12
    • 33748565956 scopus 로고    scopus 로고
    • Exact lower bound for the number of switches in series to implement a combinational logic cell
    • F. R. Schneider, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, "Exact lower bound for the number of switches in series to implement a combinational logic cell," in Proc. Int. Conf. Comput. Design, 2005, pp. 357-362.
    • (2005) Proc. Int. Conf. Comput. Design , pp. 357-362
    • Schneider, F.R.1    Ribas, R.P.2    Sapatnekar, S.S.3    Reis, A.I.4
  • 14
    • 0021965551 scopus 로고
    • A unified theory for MOS circuit design switching network logic
    • M. Wu, W. Shu, and S. Chan, "A unified theory for MOS circuit design switching network logic," Int. J. Electron, vol. 58, no. 1, pp. 1-33, 1985.
    • (1985) Int. J. Electron , vol.58 , Issue.1 , pp. 1-33
    • Wu, M.1    Shu, W.2    Chan, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.