-
1
-
-
0023531730
-
Multilevel logic optimization and the rectangular covering problem
-
R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "Multilevel logic optimization and the rectangular covering problem," in Proc. Int. Conf. Comput.-Aided Design, 1987, pp. 66-69.
-
(1987)
Proc. Int. Conf. Comput.-Aided Design
, pp. 66-69
-
-
Brayton, R.K.1
Rudell, R.2
Sangiovanni-Vincentelli, A.3
Wang, A.4
-
2
-
-
0026206707
-
Near optimal factorization of Boolean functions
-
Aug
-
G. Caruso, "Near optimal factorization of Boolean functions," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 8, pp. 1072-1078, Aug. 1991.
-
(1991)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.10
, Issue.8
, pp. 1072-1078
-
-
Caruso, G.1
-
3
-
-
33750929909
-
Fast disjoint transistor networks from BDDs
-
L. S. Da Rosa, Jr., F. S. Marques, T. M. G. Cardoso, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, "Fast disjoint transistor networks from BDDs," in Proc. 19th Annu. Symp. Integr. Circuits Syst. Design, 2006, pp. 137-142.
-
(2006)
Proc. 19th Annu. Symp. Integr. Circuits Syst. Design
, pp. 137-142
-
-
Da Rosa Jr., L.S.1
Marques, F.S.2
Cardoso, T.M.G.3
Ribas, R.P.4
Sapatnekar, S.S.5
Reis, A.I.6
-
5
-
-
0031342379
-
Library-less synthesis for static CMOS combinational logic circuits
-
S. Gavrilov, A. Glebov, S. Pullela, S. C. Moore, A. Dharchoudhury, R. Panda, G. Vijayan, and D. T. Blaauw, "Library-less synthesis for static CMOS combinational logic circuits," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 1997, pp. 658-662.
-
(1997)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 658-662
-
-
Gavrilov, S.1
Glebov, A.2
Pullela, S.3
Moore, S.C.4
Dharchoudhury, A.5
Panda, R.6
Vijayan, G.7
Blaauw, D.T.8
-
8
-
-
0033365094
-
Transistor level synthesis for static CMOS combinational circuits
-
C. R. Liu and J. A. Abraham, "Transistor level synthesis for static CMOS combinational circuits," in Proc. Great Lakes Symp. VLSI, 1999, pp. 172-175.
-
(1999)
Proc. Great Lakes Symp. VLSI
, pp. 172-175
-
-
Liu, C.R.1
Abraham, J.A.2
-
10
-
-
33750925327
-
Unified theory to build cell-level transistor networks from BDDs
-
R. E. B. Poli, F. R. Schneider, R. P. Ribas, and A. I. Reis, "Unified theory to build cell-level transistor networks from BDDs," in Proc. Symp. Integr. Circuits Syst. Design, 2002, pp. 199-204.
-
(2002)
Proc. Symp. Integr. Circuits Syst. Design
, pp. 199-204
-
-
Poli, R.E.B.1
Schneider, F.R.2
Ribas, R.P.3
Reis, A.I.4
-
11
-
-
15044339296
-
Transistor-level optimization of digital designs with flex cells
-
Feb
-
R. Roy, D. Bhattacharya, and V. Boppana, "Transistor-level optimization of digital designs with flex cells," Computer, vol. 38, no. 2, pp. 53-61, Feb. 2005.
-
(2005)
Computer
, vol.38
, Issue.2
, pp. 53-61
-
-
Roy, R.1
Bhattacharya, D.2
Boppana, V.3
-
12
-
-
33748565956
-
Exact lower bound for the number of switches in series to implement a combinational logic cell
-
F. R. Schneider, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, "Exact lower bound for the number of switches in series to implement a combinational logic cell," in Proc. Int. Conf. Comput. Design, 2005, pp. 357-362.
-
(2005)
Proc. Int. Conf. Comput. Design
, pp. 357-362
-
-
Schneider, F.R.1
Ribas, R.P.2
Sapatnekar, S.S.3
Reis, A.I.4
-
14
-
-
0021965551
-
A unified theory for MOS circuit design switching network logic
-
M. Wu, W. Shu, and S. Chan, "A unified theory for MOS circuit design switching network logic," Int. J. Electron, vol. 58, no. 1, pp. 1-33, 1985.
-
(1985)
Int. J. Electron
, vol.58
, Issue.1
, pp. 1-33
-
-
Wu, M.1
Shu, W.2
Chan, S.3
-
15
-
-
0027612243
-
On the optimization of MOS circuits
-
Jun
-
J. Zhu and M. Abd-El-Barr, "On the optimization of MOS circuits," IEEE Trans. Circuits Syst. I, Fundam. Theory AppI., vol. 40, no. 6, pp. 412-422, Jun. 1993.
-
(1993)
IEEE Trans. Circuits Syst. I, Fundam. Theory AppI
, vol.40
, Issue.6
, pp. 412-422
-
-
Zhu, J.1
Abd-El-Barr, M.2
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