Automatic generation of digital cell libraries

Proceedings - 15th Symposium on Integrated Circuits and Systems Design, SBCCI 2002

Volumn , Issue , 2002, Pages 265-270

  Togni, J ^a   Schneider, F R ^a   Correia, V P ^a   Ribas, R P ^a   Reis, A I ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CYTOLOGY; DESIGN; DIGITAL LIBRARIES; LIBRARIES; LOGIC DEVICES; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

AUTOMATIC GENERATION; BOOLEAN EQUATIONS; CELL DESIGN; DESIGN ENVIRONMENT; DIGITAL CELLS; MENTOR GRAPHICS; PHYSICAL LAYOUT; TRUTH TABLES;

CELLS;

EID: 77957900925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2002.1137669     Document Type: Conference Paper

References (31)

1. ABRACAD. http://www.numericaltechnologies.com/
2. M.Berkelaar, J.Jess. "Technology mapping for standard-cell generators". ICCAD, Santa Clara, 1988, pp. 470-473.
3. V. Bertacco, S. Minato, P. Verplaetse, L. Benini, G. de Micheli, "Decision Diagrams and Pass-Transistor Logic Synthesis", IWLS '97, p. 109-113.
4. R.E.Bryant. "Graph-based algorithms for Boolean function manipulation", IEEE Transactions on Computers, vol. C-35, no 8, pp. 677-691, August 1986
5. P. Buch, A. Narayan, A. R. Newton, A. Sangiovanni-Vincentelli. "On Synthesizing Pass Transistor Networks", IWLS '97, p. 101-108.
6. CADENCE (1991) Virtuoso Layout Synthesizer - LAS - User Guide. CADENCE Version 4.2, October 1991.
7. V.P. CORREIA, A.I.REIS. Classifying n-Input Boolean Functions. In: VII WORKSHOP IBERCHIP, 2001, Montevideo. IWS 2001 - VII Workshop Iberchip. 2001. p. 58.
8. V. P. Correia, F. R. Schneider, A. I. Reis. "4-Input Function Logic Synthesis for Cell Libraries". Iberchip 2002.
9. T.H.Cormen, C.E.Leiserson, R.L.Rivest. "Introduction to Algorithms". McGraw-Hill, 1990.
10. B.A.Davey, H.A.Priestley. "Introduction to Lattices and Order". Cambridge University Press, 1990.
11. DETJENS, E. et al. Technology Mapping in MIS In: IEEE ICCAD, 1987. Proceedings... Los Alamitos, California: IEEE Computer Society Press, 1987. p.116-119.
12. J.T.J. van Eijndhoven, CMOS cell generation for Logic Synthesis, proc. 1st int. conf. on ASIC (ASICON 94), Wang Yangyuan (Ed.), Beijing, China, Oct 18-21, 1994, pp. 75-78, Electr. Ind. Publ. House, Wanshou Rd., Beijing, China.
13. S.H.Gerez. "Algorithms for VLSI Design Automation". Wiley, 1999.
14. M.Guruswamy et al. Cellerity: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. In: ACM DAC, 1997, p.327.
15. T. Ibaraki, S. Muroga. "Synthesis of networks with minimum number of negative gates". IEEE Transactions on Computers, vol. C-20, No. 1, p. 49-58, 1971.
16. M.Johann. "Algoritmos para Síntese Física". Capítulo 8 em: Concepção de Circuitos Integrados. Editor: Ricardo Reis. Editora Sagra Luzzato, 2000.
17. R. H. Katz. Contemporary Logic Design. The Benjamin/Cummings Publishing Company, Inc, p. 85-89, 1995.
18. E. Lehman, Y. Watanabe, J. Grodstein, H. Harkness. "Logic Decomposition during Technology Mapping".IEEE, p. 264-271, 1995
19. F.Moraes. "Anatomia de uma ferramenta de Síntese Automática de Leiaute". Capítulo 10 em: Concepção de Circuitos Integrados. Editor: Ricardo Reis. Editora Sagra Luzzato, 2000.
20. F.Moraes, N.Azemard, M.Robert, D.Auvergne. "Flexible Macrocell Layout Generator", Proc. of 4th ACM/SIGDA Physical Design Workshop, 1993, Los Angeles (USA), pp. 105-116.
21. S.Muroga. Procedure 4.2.1: Design of Logic Networks with Negative Gates in Single-Rail Input Logic. In: VLSI System Design: When and How to Design Very-Large-Scale Integrated Circuits. John Wiley & Sons. 1979.
22. K.Nakamura et al. Minimal Negative Gate Networks. IEEE Transactions on Computers, Vol. C-21, No. 1, January 1972.
23. K.Nakamura. Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks. IEEE Transactions on Computers, Vol. C-28, No. 10, October 1979.
24. www.prolificinc.com
25. A.Reis. "Síntese Lógica". Capítulo 7 em: Concepção de Circuitos Integrados. Editor: Ricardo Reis. Editora Sagra Luzzato, 2000.
26. A. Reis, R. Reis, D. Auvergne and M. Robert. "Library free technology mapping". VLSI97 - IX IFIP International Conference on Very Large Scale Integration, August 1997, Gramado, RS, Brazil.
27. T. Sasao. "Equivalence Classes of Logic Functions". In: Switching Theory for Logic Synthesis. Section 5.7. Kluwer Academic Publishers. 1999.
28. T. Sasao. "Lattice and Boolean Algebra". In: Switching Theory for Logic Synthesis. Chapter 2. Kluwer Academic Publishers. 1999.
29. E.M.Sentovich, K.J.Singh, L.Lavagno et al. "SIS : A system for sequential circuit synthesis". Technical report UCB/ERL M92/41, University of California at Berkeley, 1992.
30. T.Uehara, W.M.VanCleemput. "Optimal Layout of CMOS functional Arrays". IEEE Transactions on Computers, Vol. C-30, No. 5, May 1981.
31. K. Yano, T. Sasaki, K. Rikino, K. Seki. "Top-Down Pass-Transistor Logic Degin". IEEE Journal of Solid-State Circuits, vol. 31, No. 6, p. 792-803, 1996.