-
2
-
-
0003934798
-
-
Tech. Rep. UCB/ERL M92/41. UC Berkeley Berkely
-
E. Sentovich, K. Singh, L.Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton and A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41. UC Berkeley, Berkely, 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
-
-
Sentovich, E.1
Singh, K.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.8
Brayton, R.9
Sangiovanni-Vincentelli, A.10
-
4
-
-
33846545005
-
-
Mishchenko, A., Chatterjee, S., and Brayton, R. DAGaware AIG rewriting a fresh look at combinational logic synthesis. DAC '06, 532-535.
-
DAGaware AIG Rewriting A Fresh Look at Combinational Logic Synthesis DAC '06
, pp. 532-535
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
-
5
-
-
0043092192
-
Large-scale SOP minimization using decomposition and functional properties
-
Mishchenko, A. and Sasao, T. 2003. Large-scale SOP minimization using decomposition and functional properties. DAC '03, 149-154.
-
(2003)
DAC '03
, pp. 149-154
-
-
Mishchenko, A.1
Sasao, T.2
-
6
-
-
0033347266
-
-
IEE Press, Piscataway, NJ
-
M.C. Golumbic and A. Mintz, Factoring Logic Functions Using Graph Partitioning, ICCAD '99. IEE Press, Piscataway, NJ, 195-199.
-
Factoring Logic Functions Using Graph Partitioning, ICCAD '99
, pp. 195-199
-
-
Golumbic, M.C.1
Mintz, A.2
-
7
-
-
79959256396
-
-
IWLS2003. No more counting of Literals. Presentation of discussion Group 3 at IWLS 2003
-
IWLS2003. No more counting of Literals. Presentation of discussion Group 3 at IWLS 2003. Available at: www.sigda.org/iwls/iwls2003/no-more
-
-
-
-
8
-
-
33745823396
-
FRAIGs: A Unifying representation for logic synthesis and verification
-
EECS Dept., UC Berkeley March
-
A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton, "FRAIGs: A Unifying Representation for Logic Synthesis and Verification ", ERL Technical Report, EECS Dept., UC Berkeley, March 2005.
-
(2005)
ERL Technical Report
-
-
Mishchenko, A.1
Chatterjee, S.2
Jiang, R.3
Brayton, R.4
-
9
-
-
79959242781
-
Constructive AIG Optimization through Functional Composition
-
Como, Italy-February
-
T. Figueiro, R. P. Ribas, A. I. Reis, Constructive AIG Optimization through Functional Composition, 1st ERDIAP Workshop: Exploiting Regularity in the De sign of IPs, Architectures and Platforms. Como, Italy-February 23, 2011.
-
(2011)
1st ERDIAP Workshop: Exploiting Regularity in the de Sign of IPs, Architectures and Platforms
, vol.23
-
-
Figueiro, T.1
Ribas, R.P.2
Reis, A.I.3
-
10
-
-
0032681920
-
Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
-
NY
-
Cong, J., Wu, C., and Ding, Y. 1999. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. FPGA '99, NY, 29-35.
-
(1999)
FPGA '99
, pp. 29-35
-
-
Cong, J.1
Wu, C.2
Ding, Y.3
-
11
-
-
0028259317
-
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
-
January
-
J. Cong and Y. Ding, FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs IEEE Trans. CAD, Vol.13, No. 1 (January 1994), pp. 1-12.
-
(1994)
IEEE Trans. CAD
, vol.13
, Issue.1
, pp. 1-12
-
-
Cong, J.1
Ding, Y.2
-
12
-
-
39749174191
-
Factor cuts
-
Chatterjee, S., Mishchenko, A., and Brayton, R. Factor cuts. ICCAD '06, 143-150.
-
ICCAD '06
, pp. 143-150
-
-
Chatterjee, S.1
Mishchenko, A.2
Brayton, R.3
-
13
-
-
77953103647
-
KL-Cuts: A new approach for logic synthesis targeting multiple output Blocks
-
Osvaldo Martinello Jr, Felipe S. Marques, Renato P. Ribas, André I. Reis. KL-Cuts: A New Approach for Logic Synthesis Targeting Multiple Output Blocks. DATE 2010, pp. 777-782.
-
(2010)
DATE
, pp. 777-782
-
-
Martinello Jr., O.1
Marques, F.S.2
Ribas, R.P.3
Reis, A.I.4
-
14
-
-
49749130486
-
High-quality circuit synthesis for modern Technologies
-
Lech Jozwiak," Artur Chojnacki, Aleksander Slusarczyk, "High-Quality Circuit Synthesis for Modern Technologies " ISQED 2008, pp.168-173.
-
(2008)
ISQED
, pp. 168-173
-
-
Jozwiak, L.1
Chojnacki, A.2
Slusarczyk, A.3
-
15
-
-
78650727962
-
Boolean factoring with multi-objective goals
-
M.G.A.Martins, A.B.Rasmussen, L.S.Rosa Jr., R.P. Ribas and A.I.Reis., Boolean Factoring with Multi-Objective Goals. ICCD2010, pp. 229-234.
-
ICCD 2010
, pp. 229-234
-
-
Martins, M.G.A.1
Rasmussen, A.B.2
Rosa Jr., L.S.3
Ribas, R.P.4
Reis, A.I.5
-
16
-
-
0018060164
-
Algorithm for minimal TANT network generation
-
Lee, H.-. 1978. An Algorithm for Minimal TANT Network Generation. IEEE Trans. Comput. 27, 12 (Dec. 1978), 1202-1206. (Pubitemid 9404561)
-
(1978)
IEEE Transactions on Computers
, vol.C-27
, Issue.12
, pp. 1202-1206
-
-
Lee, H.-P.S.1
|