메뉴 건너뛰기




Volumn , Issue , 2011, Pages 769-776

Constructive AIG optimization considering input weights

Author keywords

And Inverter Graph; Design Automation; Functional Composition; Logic Synthesis

Indexed keywords

AND-INVERTER GRAPH; BOTTOM UP APPROACH; DESIGN AUTOMATION; FUNCTIONAL COMPOSITION; INPUT NODE; INPUT WEIGHTS; LARGE CIRCUITS; LOGIC SYNTHESIS; SIGNAL DELAYS; SYNTHESIS ALGORITHMS; TECHNOLOGY INDEPENDENT;

EID: 79959248098     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770816     Document Type: Conference Paper
Times cited : (4)

References (16)
  • 5
    • 0043092192 scopus 로고    scopus 로고
    • Large-scale SOP minimization using decomposition and functional properties
    • Mishchenko, A. and Sasao, T. 2003. Large-scale SOP minimization using decomposition and functional properties. DAC '03, 149-154.
    • (2003) DAC '03 , pp. 149-154
    • Mishchenko, A.1    Sasao, T.2
  • 7
    • 79959256396 scopus 로고    scopus 로고
    • IWLS2003. No more counting of Literals. Presentation of discussion Group 3 at IWLS 2003
    • IWLS2003. No more counting of Literals. Presentation of discussion Group 3 at IWLS 2003. Available at: www.sigda.org/iwls/iwls2003/no-more
  • 8
    • 33745823396 scopus 로고    scopus 로고
    • FRAIGs: A Unifying representation for logic synthesis and verification
    • EECS Dept., UC Berkeley March
    • A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton, "FRAIGs: A Unifying Representation for Logic Synthesis and Verification ", ERL Technical Report, EECS Dept., UC Berkeley, March 2005.
    • (2005) ERL Technical Report
    • Mishchenko, A.1    Chatterjee, S.2    Jiang, R.3    Brayton, R.4
  • 10
    • 0032681920 scopus 로고    scopus 로고
    • Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
    • NY
    • Cong, J., Wu, C., and Ding, Y. 1999. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. FPGA '99, NY, 29-35.
    • (1999) FPGA '99 , pp. 29-35
    • Cong, J.1    Wu, C.2    Ding, Y.3
  • 11
    • 0028259317 scopus 로고
    • FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
    • January
    • J. Cong and Y. Ding, FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs IEEE Trans. CAD, Vol.13, No. 1 (January 1994), pp. 1-12.
    • (1994) IEEE Trans. CAD , vol.13 , Issue.1 , pp. 1-12
    • Cong, J.1    Ding, Y.2
  • 13
    • 77953103647 scopus 로고    scopus 로고
    • KL-Cuts: A new approach for logic synthesis targeting multiple output Blocks
    • Osvaldo Martinello Jr, Felipe S. Marques, Renato P. Ribas, André I. Reis. KL-Cuts: A New Approach for Logic Synthesis Targeting Multiple Output Blocks. DATE 2010, pp. 777-782.
    • (2010) DATE , pp. 777-782
    • Martinello Jr., O.1    Marques, F.S.2    Ribas, R.P.3    Reis, A.I.4
  • 14
    • 49749130486 scopus 로고    scopus 로고
    • High-quality circuit synthesis for modern Technologies
    • Lech Jozwiak," Artur Chojnacki, Aleksander Slusarczyk, "High-Quality Circuit Synthesis for Modern Technologies " ISQED 2008, pp.168-173.
    • (2008) ISQED , pp. 168-173
    • Jozwiak, L.1    Chojnacki, A.2    Slusarczyk, A.3
  • 16
    • 0018060164 scopus 로고
    • Algorithm for minimal TANT network generation
    • Lee, H.-. 1978. An Algorithm for Minimal TANT Network Generation. IEEE Trans. Comput. 27, 12 (Dec. 1978), 1202-1206. (Pubitemid 9404561)
    • (1978) IEEE Transactions on Computers , vol.C-27 , Issue.12 , pp. 1202-1206
    • Lee, H.-P.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.