Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 1233-1238

  Cong, Jason ^a   Zhang, Peng ^a   Zou, Yi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

data reuse; high level synthesis; loop transformation; memory hierarchy optimization

Indexed keywords

APPLICATION SYSTEMS; BANDWIDTH CONSUMPTION; BRANCH AND BOUNDS; COMPUTATION COMPLEXITY; DATA REUSE; HIGH LEVEL SYNTHESIS; LOOP FUSION; LOOP TRANSFORMATION; MEMORY HIERARCHY; NESTED LOOPS; OFF-CHIP; OFF-CHIP MEMORIES; ON CHIP MEMORY; ON-CHIP BUFFERS; OPTIMAL SOLUTIONS;

BANDWIDTH; COMPUTER AIDED DESIGN; DATA FLOW ANALYSIS; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS;

OPTIMIZATION;

EID: 84863555595     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228586     Document Type: Conference Paper

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