Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: A geometric programming framework

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 305-315

  Liu, Qiang ^a   Constantinides, George A ^a   Masselos, Konstantinos ^b   Cheung, Peter Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PELOPONNESE   (Greece)

Author keywords

Data reuse; Data level parallelization; Fieldprogrammable gate array (FPGA) hardware compilation; Geometric programming; Optimization

Indexed keywords

DATA REUSE; DESIGN SPACES; GEOMETRIC PROGRAMMING; HARDWARE COMPILATION; MEMORY RESOURCES; NON-LINEAR OPTIMIZATION; NONLINEAR PROGRAMS; OFF-CHIP MEMORIES; ON CHIP MEMORY; ON CHIPS; OPTIMAL DESIGN; PARALLELIZATIONS; SOLUTION TECHNIQUES; TWO STAGE OPTIMIZATIONS; TWO-STAGE METHODS;

DESIGN; GEOMETRY; OPTIMAL SYSTEMS;

OPTIMIZATION;

EID: 77955224068     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (31)

1. T. Todman, G. Constantinides, S. Wilton, P. Cheung, W. Luk, and O. Mencer, "Reconfigurable computing: Architectures and design methods," Proc. Inst. Elect. Eng. - Comput. Digit. Tech., vol. 152, no. 2, pp. 193-207, Mar. 2005.
2. F. Catthoor, E. de Greef, and S. Suytack, Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Norwell, MA: Kluwer, 1998.
3. Q. Liu, K. Masselos, and G. A. Constantinides, "Data reuse exploration for FPGA based platforms applied to the full search motion estimation algorithm," in Proc. FPL, Madrid, Spain, Aug. 2006, pp. 389-394.
4. Q. Liu, G. A. Constantinides, K. Masselos, and P. Y. K. Cheung, "Automatic on-chip memory minimization for data reuse," in Proc. FCCM, Napa, CA, Apr. 2007, pp. 389-394.
5. Q. Liu, G. A. Constantinides, K. Masselos, and P. Y. K. Cheung, "Data reuse exploration under area constraints for low power reconfigurable systems," in Proc. WASP, 2007.
6. U. K. Banerjee, Loop Parallelization. Norwell, MA: Kluwer, 1994.
7. N. Baradaran and P. C. Diniz, "A register allocation algorithm in the presence of scalar replacement for fine-grain configurable architectures," in Proc. DATE, 2005, pp. 6-11.
8. N. Baradaran, J. Park, and P. C. Diniz, "Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks," in Proc. FPT, 2004, pp. 145-152. (Pubitemid 40859493)
9. Z. Guo, B. Buyukkurt, and W. Najjar, "Input data reuse in compiling window operations onto reconfigurable hardware," SIGPLAN Not., vol. 39, no. 7, pp. 249-256, Jul. 2004.
10. R. P. Wilson, R. S. French, C. S. Wilson, S. P. Amarasinghe, J. M. Anderson, S. W. K. Tjiang, S.-W. Liao, C.-W. Tseng, M. W. Hall, M. S. Lam, and J. L. Hennessy, "SUIF: An infrastructure for research on parallelizing and optimizing compilers," SIGPLAN Not., vol. 29, no. 12, pp. 31-37, Dec. 1994.
11. M. Wolfe, "More iteration space tiling," in Proc. ACM/IEEE Conf. Supercomput., New York, 1989, pp. 655-664.
12. S. Boyd and L. Vandenberghe, Convex Optimization. Cambridge, U.K.: Cambridge Univ. Press, 2004.
13. M. Kandemir, G. Chen, and F. Li, "Maximizing data reuse for minimizing memory space requirements and execution cycles," in Proc. ASPDAC, Piscataway, NJ, 2006, pp. 808-813.
14. M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh, "A compiler-based approach for dynamically managing scratch-pad memories in embedded systems," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 2, pp. 243-260, Feb. 2004.
15. S. Udayakumaran and R. Barua, "Compiler-decided dynamic memory allocation for scratch-pad based embedded systems," in Proc. CASES, New York, 2003, pp. 276-286.
16. M. Weinhardt and W. Luk, "Memory access optimization for reconfigurable systems," Proc. Inst. Elect. Eng. - Comput. Digit. Tech., pp. 105-112, 2001.
17. V. Lefebvre and P. Feautrier, "Automatic storage management for parallel programs," Parallel Comput., vol. 24, no. 3/4, pp. 649-671, May 1998.
18. M. Gupta and P. Banerjee, "Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers," IEEE Trans. Parallel Distrib. Syst., vol. 3, no. 2, pp. 179-193, Mar. 1992.
19. G. M. Megson and X. Chen, Automatic Parallelization for A Class of Regular Computations. Singapore: World Scientific, 1997.
20. H. El-Rewini and M. Abd-El-Barr, Advanced Computer Architecture and Parallel Processing (Wiley Series on Parallel and Distributed Computing). New York: Wiley-Interscience, 2005.
21. U. Eckhardt and R. Merker, "Hierarchical algorithm partitioning at system level for an improved utilization of memory structures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 1, pp. 14-24, Jan. 1999.
22. N. Baradaran and P. C. Diniz, "Memory parallelism using custom array mapping to heterogeneous storage structures," in Proc. FPL, Madrid, Spain, Aug. 2006, pp. 383-388.
23. I. Issenin, E. Brockmeyer, B. Durinck, and N. Dutt, "Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies," in Proc. DAC, 2006, pp. 49-52.
24. M. Dasygenis, N. Kroupis, K. Tatas, A. Argyriou, D. Soudris, and A. Thanailakis, "Power and performance exploration of embedded systems executing multimedia kernels," Proc. Inst. Elect. Eng. - Comput. Digit. Tech., vol. 149, no. 4, pp. 164-172, Jul. 2002.
25. "Cray computer systems," CFT77 Reference Manual, Cray Res., Mendota Heights, MN, 1987. Publication SR 0018A.
26. Handel-C Language Reference Manual, Aug. 2006. [Online]. Available: http://www.celoxica.com
27. P. Vanbroekhoven, G. Janssens, M. Bruynooghe, and F. Catthoor, "A practical dynamic single assignment transformation," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 4, p. 40, Sep. 2007.
28. J. Lofberg, "Yalmip: A toolbox for modeling and optimization in MATLAB," in Proc. IEEE Int. Symp. Comput. Aided Control Syst. Des., Taipei, Taiwan, 2004, pp. 284-289.
29. V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures. Norwell, MA: Springer-Verlag, 1997.
30. 2006. [Online]. Available: http://www.pages.drexel.edu/weg22/edge.html
31. J. D. Hall, N. A. Carr, and J. C. Hart, "Cache and bandwidth aware matrix multiplication on the GPU," UIUC, Urbana, IL, Tech. Rep. UIUCDCSR- 2003-2328, 2003.