Incremental hierarchical memory size estimation for steering of loop transformations

ACM Transactions on Design Automation of Electronic Systems

Volumn 12, Issue 4, 2007, Pages

  Hu, Q ^a   Kjeldsberg, P G ^a   Vandecappelle, A ^b,c   Palkovic, M ^b,c   Catthoor, F ^b,c  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^b Imec   (Belgium)

^c IMEC   (Belgium)

Author keywords

Code transformation; Data optimization; High level synthesis; Memory architecture exploration; Memory size estimation

Indexed keywords

CODE TRANSFORMATION; DATA OPTIMIZATION; HIGH-LEVEL SYNTHESIS; MEMORY ARCHITECTURE EXPLORATION; MEMORY SIZE ESTIMATION;

EMBEDDED SYSTEMS; MATHEMATICAL TRANSFORMATIONS; MULTIMEDIA SYSTEMS; OPTIMIZATION; REAL TIME SYSTEMS; TELECOMMUNICATION SYSTEMS;

DATA STORAGE EQUIPMENT;

EID: 35148879778     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1278349.1278363     Document Type: Article

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