Bundled execution of recurring traces for energy-efficient general purpose processing

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 12-23

  Gupta, Shantanu ^a,b   Feng, Shuguang ^b   Ansari, Amin ^b   Mahlke, Scott ^b   August, David ^c  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c Princeton University   (United States)

Author keywords

co processor; efficiency; energy saving; microarchitecture

Indexed keywords

APPLICATION SPECIFIC HARDWARES; AVERAGE ENERGY; CO-PROCESSORS; ENERGY EFFICIENT; EXECUTION MODEL; GENERAL PURPOSE; INSTRUCTION FETCH; MEDIA APPLICATION; MICRO ARCHITECTURES; OFF-LOADING; POWER BUDGETS; POWER CONSTRAINTS; PROCESSING RESOURCES; PROGRAM EXECUTION; REDUCED-COMPLEXITY; REGISTER FILES; SINGLE CHIPS; TECHNOLOGY SCALING; VOLTAGE-SCALING;

EFFICIENCY; ENERGY CONSERVATION; ENERGY UTILIZATION;

ENERGY EFFICIENCY;

EID: 84863374615     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155623     Document Type: Conference Paper

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