Reconciling specialization and flexibility through compound circuits

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 277-288

  Yehia, Sami ^a   Girbal, Sylvain ^a   Berry, Hugues ^b   Temam, Olivier ^b  

^a THALES RESEARCH AND TECHNOLOGY   (France)

^b INRIA SACLAY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; EFFICIENCY; EMBEDDED SYSTEMS; MULTICORE PROGRAMMING; SCALABILITY; TIMING CIRCUITS;

AGGREGATION METHODS; CONFIGURATION COSTS; COST-EFFICIENT; INDIVIDUAL CUSTOMIZATION; IS FLEXIBILITY; POWER EFFICIENCY; TARGET APPLICATION; TARGET CIRCUITS;

BENCHMARKING;

EID: 64949084227     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798263     Document Type: Conference Paper

References (28)

1. Synopsys design compiler. http://www.synopsys.com.
2. Tensilica. http://www.tensilica.com/.
3. Virtex-5 multi-platform fpga. http://www.xilinx.com/products/silicon- solutions/fpgas/virtex/.
4. Designing high-performance dsp hardware using Catapult C synthesis and the altera accelerated libraries. Mentor Graphics Technical Library, October 2007.
5. G. Ansaloni, P. Bonzini, and L. Pozzi. Design and architectural exploration of expression-grained reconfigurable arrays. In Proc. of the 6th IEEE Symposium on Application Specific Processors, 2008.
6. D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. A. Penry, O. Temam, and N. Vachharajani. Unisim: An open simulation environment and library for complex architecture design and collaborative development. IEEE Comput. Archit. Lett., 6(2):45-48, 2007.
7. P. Brisk, A. Kaplan, and M. Sarrafzadeh. Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 395-400, New York, NY, USA, 2004. ACM.
8. M. Budiu, G. Venkataramani, T. Chelcea, and S. C. Goldstein. Spatial computation. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 14-26, Boston, MA, October 2004.
9. A. C.-H. Cheng. Application-specific architecture framework for high-performance low-power embedded computing. PhD thesis, Ann Arbor, MI, USA, 2006.
10. S. Ciricescu, R. Essick, B. Lucas, P. May, K. Moat, J. Norris, M. Schuette, and A. Saidi. The reconfigurable streaming vector processor (rsvptm). In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, page 141, Washington, DC, USA, 2003. IEEE Computer Society.
11. N. Clark et al. Application-specific processing on a generalpurpose core via transparent instruction set customization. In Proc. of the International Symposium on Microarchitecture, pages 30-40, 2004.
12. N. Clark et al. OptimoDE: Programmable accelerator engines through retargetable customization, 2004. In Proc. of Hot Chips 16.
13. N. Clark, A. Hormati, and S. Mahlke. Veal: Virtualized execution accelerator for loops. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 389-400, Washington, DC, USA, 2008. IEEE Computer Society.
14. K. De Jong. Evolutionary Computation: A Unified Approach. MIT Press, 2006.
15. IBM. PowerPC 405 CPU Core. Sept. 2006.
16. N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Archit. News, 18(3a):364-373, 1990.
17. C. G. Lee. UTDSP benchmark suite. http://www.eecg.toronto.edu/ ̃corinna/DSP/infrastructure/UTDSP.html, 1998.
18. Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner. Soda: A low-power architecture for software radio. In ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, pages 89-101, Washington, DC, USA, 2006. IEEE Computer Society.
19. B. Mathew and A. Davis. A loop accelerator for low power embedded vliw processors. In CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 6-11, New York, NY, USA, 2004. ACM.
20. M. Mishra, T. J. Callahan, T. Chelcea, G. Venkataramani, M. Budiu, and S. C. Goldstein. Tartan: Evaluating spatial computation for whole program execution. In 12th ACM International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), pages 163-174, San Jose, CA, 2006.
21. N. Moreano, E. Borin, C. de Souza, and G. Araujo. Efficient datapath merging for partially reconfigurable architectures. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 24(7):969-980, July 2005.
22. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. SIGARCH Comput. Archit. News, 31(2):422-433, 2003.
23. R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist, and M. Sivaraman. Pico-npa: High-level synthesis of nonprogrammable hardware accelerators. J. VLSI Signal Process. Syst., 31(2):127-142, 2002.
24. L. Shang and N. Jha. High-level power modeling of cplds and fpgas. Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, pages 46-51, 2001.
25. M. Stephenson, J. Babb, and S. Amarasinghe. Bidwidth analysis with application to silicon compilation. In PLDI '00: Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, pages 108-120, New York, NY, USA, 2000. ACM.
26. A. K. Verma, P. Brisk, and P. Ienne. Progressive decomposition: a heuristic to structure arithmetic circuits. In DAC '07: Proceedings of the 44th annual conference on Design automation, pages 404-409, New York, NY, USA, 2007. ACM.
27. S. Yehia and O. Temam. From sequences of dependent instructions to functions: An approach for improving performance without ILP or speculation. In ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, page 238, Washington, DC, USA, 2004. IEEE Computer Society.
28. M. Zuluaga and N. Topham. Resource sharing in custom instruction set extensions. In Proc. of the 6th IEEE Symposium on Application Specific Processors, 2008.