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Volumn 33, Issue 4, 2012, Pages 474-476

Variability origins of parasitic resistance in finFETs with silicided source/drain

Author keywords

Fin shaped FET (FinFET); NiSi; parasitic resistance (R para); scaling; source drain (S D); variability

Indexed keywords

FIN-SHAPED FET (FINFET); NISI; PARASITIC RESISTANCES; SCALING; SOURCE/DRAIN (S/D); VARIABILITY;

EID: 84862816937     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2182755     Document Type: Article
Times cited : (15)

References (13)
  • 7
    • 33646510845 scopus 로고    scopus 로고
    • Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions
    • Apr.
    • A. Dixit, K. G. Anil, R. Rooyackers, F. Lays, M. Kaiser, N. Collaert, K. De Meyer, M. Jurczak, and S. Biesemans, " Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions, " Solid State Electron., vol. 50, no. 4, pp. 587-593, Apr. 2006.
    • (2006) Solid State Electron. , vol.50 , Issue.4 , pp. 587-593
    • Dixit, A.1    Anil, K.G.2    Rooyackers, R.3    Lays, F.4    Kaiser, M.5    Collaert, N.6    De Meyer, K.7    Jurczak, M.8    Biesemans, S.9
  • 10
    • 79951958788 scopus 로고    scopus 로고
    • Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs
    • Mar.
    • M. Saitoh, Y. Nakabayashi, K. Uchida, and T. Numata, " Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs, " IEEE Electron Device Lett., vol. 32, no. 3, pp. 273-275, Mar. 2011.
    • (2011) IEEE Electron Device Lett. , vol.32 , Issue.3 , pp. 273-275
    • Saitoh, M.1    Nakabayashi, Y.2    Uchida, K.3    Numata, T.4
  • 13
    • 54849361900 scopus 로고    scopus 로고
    • Demonstration of Schottky barrier NMOS TransistorsWith Erbium silicided source/drain and silicon nanowire channel
    • Oct.
    • E. J. Tan, K.-L. Pey, N. Singh, G.-Q. Lo, D. Z. Chi, Y. K. Chin, K. M. Hoe, G. Cui, and P. S. Lee, " Demonstration of Schottky barrier NMOS TransistorsWith Erbium silicided source/drain and silicon nanowire channel, " IEEE Electron Device Lett., vol. 29, no. 10, pp. 1167-1170, Oct. 2008.
    • (2008) IEEE Electron Device Lett. , vol.29 , Issue.10 , pp. 1167-1170
    • Tan, E.J.1    Pey, K.-L.2    Singh, N.3    Lo, G.-Q.4    Chi, D.Z.5    Chin, Y.K.6    Hoe, K.M.7    Cui, G.8    Lee, P.S.9


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.