An ultralow-resistance ultrashallow metallic source/drain contact scheme for III-V NMOS

IEEE Electron Device Letters

Volumn 33, Issue 4, 2012, Pages 501-503

  Oxland, R ^a   Chang, S W ^a   Li, Xu ^b   Wang, S W ^a   Radhakrishnan, G ^c   Priyantha, W ^c   Van Dal, M J H ^a   Hsieh, C H ^d   Vellianitis, G ^a   Doornbos, G ^a   Bhuwalka, K ^a   Duriez, B ^a   Thayne, I ^b   Droopad, R ^c   Passlack, M ^a   Diaz, C H ^d   Sun, Y C ^d  

^a TSMC R and D Europe BV   (Belgium)

^b UNIVERSITY OF GLASGOW   (United Kingdom)

^c TEXAS STATE UNIVERSITY   (United States)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

High mobility channel; III V semiconductor materials; MOSFETs; semiconductor metal interfaces

Indexed keywords

FULLY SELF-ALIGNED; HIGH MOBILITY; II-IV SEMICONDUCTORS; INAS; JUNCTION DEPTH; MOSFETS; PERFORMANCE METRICS; SEMICONDUCTOR-METAL INTERFACES; SPECIFIC CONTACT RESISTIVITY;

INDIUM ARSENIDE; INTERFACES (MATERIALS); SEMICONDUCTOR JUNCTIONS;

VANADIUM;

EID: 84862807877     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2185919     Document Type: Article

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