30-nm InAs PHEMTs with fT = 644 GHz and fmax = 681 GHz

IEEE Electron Device Letters

Volumn 31, Issue 8, 2010, Pages 806-808

  Kim, Dae Hyun ^a,b   Del Alamo, Jess A ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b TELEDYNE SCIENTIFIC COMPANY   (United States)

Author keywords

Cutoff frequency (fT); InAs; maximum oscillation frequency (f max); pseudomorphic HEMTs (PHEMTs); short channel effects; side recess spacing (Lside)

Indexed keywords

INAS; INP SUBSTRATES; MATERIAL SYSTEMS; MAXIMUM OSCILLATION FREQUENCY; PSEUDOMORPHIC HEMTS (PHEMTS); SHORT-CHANNEL EFFECT; SOURCE AND DRAIN RESISTANCE;

ELECTRIC CONTACTORS; HETEROJUNCTION BIPOLAR TRANSISTORS; HIGH ELECTRON MOBILITY TRANSISTORS; OHMIC CONTACTS; SEMICONDUCTING INDIUM;

CUTOFF FREQUENCY;

EID: 77955172642     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2051133     Document Type: Article

References (14)

1. R. Lai, X. B. Mei, W. R. Deal, W. Yoshida, Y. M. Kim, P. H. Liu, J. Lee, J. Uyeda, V. Radisic, M. Lange, T. Gaier, L. Samoska, and A. Fung, "Sub 50 nm InP HEMT device with fmax greater than 1 THz," in IEDM Tech. Dig., 2007, pp. 609-612.
2. D.-H. Kim and J. A. del Alamo, "30-nm InAs pseudomorphic HEMTs on an InP substrate with a current-gain cutoff frequency of 628 GHz," IEEE Electron Device Lett., vol.29, no.8, pp. 830-833, Aug. 2008.
3. D.-H. Kim and J. A. del Alamo, "30-nm E-mode InAs PHEMTs for THz and future logic applications," in IEDM Tech. Dig., 2008, pp. 719-722.
4. W. Snodgrass, W. Hafez, N. Harff, and M. Feng, "Pseudomorphic InP/InGaAs heterojunction bipolar transistors (PHBTs) experimentally demonstrating fT = 765 GHz at 25 ° C increasing to fT = 845 GHz at\55 °C," in IEDM Tech. Dig., 2006, pp. 595-598.
5. Z. Griffith, E. Lind, and M. J. W. Rodwell, "Sub-300 nm InGaAs/InP type-I DHBTs with a 150 nm collector, 30 nm base demonstrating 755 GHz fmax and 416 GHz fT," in Proc. IEEE Int. Conf. IPRM, 2007, pp. 403-406.
6. A. Endoh, Y. Yamashita, K. Shinohara, K. Hikosaka, T. Matsui, S. Hiyamizu, and T. Mimura, "InP-based high electron mobility transistors with a very short gate-channel distance," Jpn. J. Appl. Phys., vol. 42, no. 4B, pp. 2214-2218, Apr. 2003.
7. K. Shinohara, Y. Yamashita, A. Endoh, I. Watanabe, K. Hikosaka, T. Matsui, T. Mimura, and S. Hiyamizu, "547 GHz ft In0.7Ga0.3As/In0.52Al0.48As HEMTs with reduced source and drain resistance," IEEE Electron Device Lett., vol.25, no.5, pp. 241-243, May 2004.
8. S. Wada, J. Yamazaki, M. Ishikawa, and T. Maeda, "An 0.1-μm void-less double-deck-shaped (DDS) gate HJFET with reduced gate-fringing- capacitance," IEEE Trans. Electron Devices, vol.46, no.5, pp. 859-864, May 1999.
9. T. Suemitsu, H. Yokoyama, T. Ishii, T. Enoki, G. Meneghesso, and E. Zanoni, "30-nm two-step recess gate InP-based InAlAs/InGaAs HEMTs," IEEE Trans. Electron Devices, vol.49, no.10, pp. 1694-1700, Oct. 2002.
10. D.-H. Kim, J. A. del Alamo, J.-H. Lee, and K.-S. Seo, "The impact of side-recess spacing on the logic performance of 50 nm In0.7Ga0.3As HEMTs," in Proc. 18th IEEE IPRM Conf., May 2006, pp. 177-180.
11. D.-H. Kim and J. A. del Alamo, "Impact of lateral engineering on the logic performance of sub-50 nm InGaAs HEMTs," in Proc. ISDRS, 2007, pp. 1-2.
12. K. Shinohara, Y. Yamashita, A. Endoh, I. Watanabe, K. Hikosaka, T. Mimura, S. Hiyamizu, and T. Matsui, "Nanogate InP-HEMT technology for ultrahigh-speed performance," in Proc. 16th IEEE IPRM Conf, 2004, pp. 721-726.
13. D. R. Greenberg and J. A. del Alamo, "Nonlinear source and drain resistance in recessed-gate heterostructure field-effect transistors," IEEE Trans. Electron Devices, vol.43, no.8, pp. 1304-1306, Aug. 1996.
14. H. K. Gummel, "On the definition of the cutoff frequency fT," Proc. IEEE, vol.57, no.12, p. 2159, Dec. 1969.