Positive bias-induced V th instability in graphene field effect transistors

IEEE Electron Device Letters

Volumn 33, Issue 3, 2012, Pages 339-341

  Liu, W J ^a   Sun, X W ^a   Fang, Z ^a   Wang, Z R ^a   Tran, X A ^a   Wang, F ^a   Wu, L ^a   Ng, G I ^a   Zhang, J F ^b   Wei, J ^c   Zhu, H L ^d   Yu, H Y ^e  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b LIVERPOOL JOHN MOORES UNIVERSITY   (United Kingdom)

^c SINGAPORE INSTITUTE OF MANUFACTURING TECHNOLOGY   (Singapore)

^d INSTITUTE OF MICROELECTRONICS   (China)

^e SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

Author keywords

1 f; Graphene field effect transistors (GFETs); reliability

Indexed keywords

1/F; 1/F NOISE; BACK-GATE; GATE LENGTH; GRAPHENE LAYERS; POSITIVE BIAS; TRAP GENERATION; TRAPPED ELECTRONS;

FIELD EFFECT TRANSISTORS; GRAPHENE; RELIABILITY;

SILICON COMPOUNDS;

EID: 84862793297     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2181150     Document Type: Article

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