Hierarchical network-on-chip and traffic compression for spiking neural network implementations

Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

Volumn , Issue , 2012, Pages 83-90

  Carrillo, S ^a   Harkin, J ^a   McDaid, L J ^a   Pande, S ^b   Cawley, S ^b   McGinley, B ^b   Morgan, F ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b NATIONAL UNIVERSITY OF IRELAND   (Ireland)

Author keywords

adaptive routing; hierarchical architecture; network topology; network on chip; spiking neural networks

Indexed keywords

ADAPTIVE ROUTING; HIERARCHICAL ARCHITECTURES; NETWORK ON CHIP; NETWORK TOPOLOGY; SPIKING NEURAL NETWORKS;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; HARDWARE; INTELLIGENT AGENTS; NETWORK ARCHITECTURE; NEURAL NETWORKS; SERVERS; VLSI CIRCUITS;

ROUTERS;

EID: 84862732015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2012.17     Document Type: Conference Paper

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