An efficient, high-throughput adaptive NoC router for large scale spiking neural network hardware implementations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6274 LNCS, Issue , 2010, Pages 133-144

  Carrillo, Snaider ^a   Harkin, Jim ^a   McDaid, Liam ^a   Pande, Sandeep ^b   Morgan, Fearghal ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b NATIONAL UNIVERSITY OF IRELAND   (Ireland)

Author keywords

Adaptive Router Architecture; EMBRACE; Network on Chip; Spiking Neural Networks

Indexed keywords

ADAPTIVE ROUTERS; ADAPTIVE ROUTING; BIOLOGICALLY INSPIRED; EMBRACE; HARDWARE IMPLEMENTATIONS; HIGH-THROUGHPUT; LOW AREA; LOW-POWER CONSUMPTION; NETWORK DELAYS; NETWORK ON CHIP; OUTPUT PORTS; PACKET THROUGHPUT; POWER CONSUMPTION; PRIORITY SCHEMES; RE-CONFIGURABLE; ROBUST COMPUTING; ROUND ROBIN; ROUTER ARCHITECTURE; SPIKING NEURAL NETWORKS; TRAFFIC LOADS;

COMPUTER ARCHITECTURE; HARDWARE; INTELLIGENT AGENTS; NETWORK ARCHITECTURE; NEURAL NETWORKS; SERVERS; THROUGHPUT; TRAFFIC CONGESTION; VLSI CIRCUITS;

ROUTERS;

EID: 78049394915     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-15323-5_12     Document Type: Conference Paper

References (16)

1. Gerstner, W.: Spiking neuron models: Single neurons, populations, plasticity. Cambridge Univ. Pr., Cambridge (2002)
2. Livi, P., Indiveri, G.: A current-mode conductance-based silicon neuron for address-event neuromorphic systems. In: 2009 IEEE International Symposium on Circuits and Systems, pp. 2898-2901. IEEE, Los Alamitos (2009)
3. Harkin, J., Morgan, F., McDaid, L., Hall, S., McGinley, B., Cawley, S.: A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks. International Journal of Reconfigurable Computing 2009, 1-13 (2009)
4. Maguire, L. P., McGinnity, T. M., Glackin, B., Ghani, A., Belatreche, A., Harkin, J.: Challenges for large-scale implementations of spiking neural networks on FPGAs. Neurocomput. 71, 13-29 (2007)
5. Shayani, H., Bentley, P., Tyrrell, A.: A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs. In: Hornby, G. S., Sekanina, L., Haddow, P. C. (eds.) ICES 2008. LNCS, vol. 5216, pp. 273-284. Springer, Heidelberg (2008)
6. Thomas, D., Luk, W.: FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. In: 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, pp. 45-52. IEEE, Los Alamitos (2009)
7. Nageswaran, J. M., Dutt, N., Krichmar, J. L., Nicolau, A., Veidenbaum, A.: Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. In: 2009 International Joint Conference on Neural Networks, pp. 2145-2152. IEEE, Los Alamitos (2009)
8. Roche, B., Mc Ginnity, T., Maguire, L., Mc Daid, L.: Signalling techniques and their effect on neural network implementation sizes. Information Sciences 132, 67-82 (2001)
9. Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. Computer 35, 70-78 (2002)
10. Theocharides, T., Link, G., Vijaykrishnan, N., Irwin, M., Srikantam, V.: A generic reconfigurable neural network architecture implemented as a network on chip. In: Proceedings of IEEE International SOC Conference 2004, pp. 191-194. IEEE, Los Alamitos (2004)
11. Philipp, S., Schemmel, J., Meier, K.: A QoS network architecture to interconnect largescale VLSI neural networks. In: 2009 International Joint Conference on Neural Networks, pp. 2525-2532. IEEE, Los Alamitos (2009)
12. Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J., Yang, S.: A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers 24, 454-463 (2007)
13. McDaid, L., Hall, S., Kelly, P.: A programmable facilitating synapse device. In: 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence), pp. 1615-1620. IEEE, Los Alamitos (2008)
14. Morgan, F., Cawley, S., Mc Ginley, B., Pande, S., Mc Daid, L., Glackin, B., Maher, J., Harkin, J.: Exploring the evolution of NoC-based Spiking Neural Networks on FPGAs. In: 2009 International Conference on Field-Programmable Technology, pp. 300-303 (2009)
15. Dally, W. J., Towles, B.: Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco (2004)
16. Pande, S., Carrillo, S., Morgan, F., Cawley, S., Harkin, J., Mc Ginley, B., McDaid, L.: EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures. Technical Report: Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC), National University of Ireland, NUI Galway, Galway, Ireland (2010)