A generic reconfigurable neural network architecture implemented as a network on chip

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2004, Pages 191-194

  Theocharides, T ^a   Link, G ^a   Vijaykrishnan, N ^a   Irwin, M J ^a   Srikantam, V ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC DEMANDS; DATA MANIPULATION; FEED FORWARD (FF); REAL TIME COMPUTATION;

ARTIFICIAL INTELLIGENCE; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA MINING; DIGITAL SIGNAL PROCESSING; INTERCONNECTION NETWORKS; PATTERN RECOGNITION; PERSONNEL TRAINING; REAL TIME SYSTEMS; SECURITY OF DATA; VIRTUAL REALITY;

NEURAL NETWORKS;

EID: 14844337467     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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