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Volumn , Issue , 2012, Pages 562-565

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC PROGRAMMING; C (PROGRAMMING LANGUAGE); PROGRAM PROCESSORS;

EID: 84862070188     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176532     Document Type: Conference Paper
Times cited : (11)

References (17)
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    • Dongwoo, L.1    Jongwhoa, N.2
  • 2
    • 80051994526 scopus 로고    scopus 로고
    • Accelerating RTL fault simulation through RTL-to-TLM abstraction
    • N. Bombieri, F. Fummi, and V. Guarnieri, "Accelerating RTL fault simulation through RTL-to-TLM abstraction," in Proc. of IEEE ETS, 2011, pp. 117-122.
    • Proc. of IEEE ETS, 2011 , pp. 117-122
    • Bombieri, N.1    Fummi, F.2    Guarnieri, V.3
  • 3
    • 39749103500 scopus 로고    scopus 로고
    • A functional coverage metric for estimating the gate-level fault coverage of functional tests
    • S. Park, L. Chen, P. K. Parvathala, S. Patil, and I. Pomeranz, "A functional coverage metric for estimating the gate-level fault coverage of functional tests," in Proc. of IEEE ITC, 2006, pp. 1-10.
    • Proc. of IEEE ITC, 2006 , pp. 1-10
    • Park, S.1    Chen, L.2    Parvathala, P.K.3    Patil, S.4    Pomeranz, I.5
  • 4
    • 33750586097 scopus 로고    scopus 로고
    • A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage
    • Z. Liang, I. Ghosh, and M. Hsiao, "A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage," IEEE Trans. on CAD, vol. 25, no. 11, pp. 2526-2538, 2006.
    • (2006) IEEE Trans. on CAD , vol.25 , Issue.11 , pp. 2526-2538
    • Liang, Z.1    Ghosh, I.2    Hsiao, M.3
  • 5
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    • P. Thaker, V. Agrawal, and M. Zaghloul, "A test evaluation technique for VLSI circuits using register-transfer level fault modeling," IEEE Trans. on CAD, vol. 22, no. 8, pp. 1104-1113, 2003.
    • (2003) IEEE Trans. on CAD , vol.22 , Issue.8 , pp. 1104-1113
    • Thaker, P.1    Agrawal, V.2    Zaghloul, M.3
  • 6
    • 51549120204 scopus 로고    scopus 로고
    • Towards acceleration of fault simulation using graphics processing units
    • K. Gulati and S. P. Khatri, "Towards acceleration of fault simulation using graphics processing units," in Proc. of ACM/IEEE DAC, 2008, pp. 822-827.
    • Proc. of ACM/IEEE DAC, 2008 , pp. 822-827
    • Gulati, K.1    Khatri, S.P.2
  • 7
    • 77954563626 scopus 로고    scopus 로고
    • Fault table computation on GPUs
    • April
    • -, "Fault table computation on GPUs," J. Electron. Test., vol. 26, pp. 195-209, April 2010.
    • (2010) J. Electron. Test. , vol.26 , pp. 195-209
    • Gulati, K.1    Khatri, S.P.2
  • 9
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  • 11
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    • Parallel cycle based logic simulation using graphics processing units
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.