A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2526-2537

  Zhang, Liang ^b   Ghosh, Indradeep ^a,c   Hsiao, Michael S ^a,d  

^a IEEE

^b CADENCE DESIGN SYSTEMS   (United States)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

^d Virginia Polytechnic Institute and State University   (United States)

Author keywords

Automatic test pattern generator (ATPG); Design validation; Deterministic and simulation based validation; Register transfer level (RTL)

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; CONTROLLABILITY; DIGITAL ARITHMETIC; ERROR ANALYSIS; HEURISTIC METHODS; OBSERVABILITY;

AUTOMATIC TEST PATTERN GENERATOR (ATPG); DESIGN VALIDATION; INDUSTRIAL BENCHMARK CIRCUITS; REGISTER TRANSFER LEVEL (RTL);

COMPUTER AIDED DESIGN;

EID: 33750586097     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.881333     Document Type: Article

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