Fault table computation on GPUs

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 26, Issue 2, 2010, Pages 195-209

  Gulati, Kanupriya ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Fault simulation; Fault table; Hardware acceleration

Indexed keywords

BIT PARALLELISM; COMPUTATIONAL POWER; CRITICAL PATH TRACING; FAULT DIAGNOSIS; FAULT DROPPING; FAULT SIMULATION; GRAPHICS PROCESSING UNIT; HARDWARE ACCELERATION; MEMORY BANDWIDTHS; NUMBER OF THREADS; PARALLEL FAULT SIMULATION; REDUCTION OPERATION; RUNTIMES; SINGLE-CORE PROCESSORS; TEST PATTERN; THREAD LEVEL PARALLELISM;

COMPUTER GRAPHICS EQUIPMENT; COMPUTER HARDWARE; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; PROGRAM PROCESSORS;

FAULT DETECTION;

EID: 77954563626     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-010-5147-x     Document Type: Conference Paper

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