Towards acceleration of fault simulation using graphics processing units

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 822-827

  Gulati, Kanupriya ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Fault simulation; Graphics Processing Units

Indexed keywords

FAULT SIMULATION; GRAPHICS PROCESSING UNITS;

CIRCUIT SIMULATION; COLOR IMAGE PROCESSING; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; IMAGE CODING; INDUSTRIAL ENGINEERING; INFORMATION THEORY;

DATA STORAGE EQUIPMENT;

EID: 51549120204     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555933     Document Type: Conference Paper

References (24)

1. P. Banerjee, Parallel Algorithms for VLSI Computer-aided Design. Prentice Hall, June 1994. ISBN-13:978-0130158352 (ISBN-10:0130158356).
2. M. B. Amin and B. Vinnakota, "Workload distribution in fault simulation," J. Electron. Test., vol. 10, no. 3, pp. 277-282, 1997.
3. A. Abramovici, Y. Levendel, and P. Menon, "A logic simulation engine," in IEEE Transactions on Computer-Aided Design, vol. 2, pp. 82-94, April 1983.
4. P. Agrawal, W. J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, and R. Tutundjian, "Mars: A multiprocessor-based programmable accelerator," IEEE Des. Test, vol. 4, no. 5, pp. 28-36, 1987.
5. V. Narayanan and V. Pitchumani, "Fault simulation on massively parallel simd machines: algorithms, implementations and results," J. Electron. Test., vol. 3, no. l,pp. 79-92, 1992.
6. S. Tai and D. Bhattacharya, "Pipelined fault simulation on parallel machines using the circuitfiow graph," in Computer Design: VLSI in Computers and Processors, pp. 564-567, Oct 1993.
7. G. F. Pfister, "The yorktown simulation engine: Introduction," in DAC '82: Proceedings of the 19th conference on Design automation, (Piscataway, NJ, USA), pp. 51-54, IEEE Press, 1982.
8. D. K. Beece, G. Deibert, G. Papp, and F. Villante, "The ibm engineering verification engine," in DAC '88: Proceedings of the 25th ACM/IEEE conference on Design automation, (Los Alamitos, CA, USA), pp. 218-224, IEEE Computer Society Press, 1988.
9. F. Ozguner and R. Daoud, "Vectorized fault simulation on the cray x-mp supercomputer," in Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on, pp. 198-201, Nov 1988.
10. F. Ozguner, C. Aykanat, and O. Khalid, "Logic fault simulation on a vector hypercube multiprocessor," in Proceedings of the third conference on Hypercube concurrent computers and applications, (New York, NY, USA), pp. 1108-1116, ACM, 1988.
11. R. Raghavan, J. Hayes, and W. Martin, "Logic simulation on vector processors," in Computer-Aided Design, Digest of Technical Papers., IEEE International Conference on, pp. 268-271, Nov 1988.
12. N. Ishiura, M. Ito, and S. Yajima, "High-speed fault simulation using a vector processor," in Proceedings of the International Conference on Computer-Aided Design ICCAD, Nov 1987.
13. M. B. Amin and B. Vinnakota, "Data parallel fault simulation," IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 7, no. 2, pp. 183-190, 1999.
14. R. Mueller-Thuns, D. Saab, R. Damiano, and J. Abraham, "VIsi logic and fault simulation on general-purpose parallel computers," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 446-460, March 1993.
15. Z. Fan, F. Qiu, A. Kaufman, and S. Yoakum-Stover, "GPU cluster for high performance computing," in SC '04: Proceedings of the 2004 ACM/IEEE conference on Supercomputing, (Washington, DC, USA), p. 47, IEEE Computer Society, 2004.
16. J. Owens, "GPU architecture overview," in SIGGRAPH '07: ACM SIGGRAPH 2007 courses, (New York, NY, USA), p. 2, ACM, 2007.
17. D. Luebke, M. Harris, N. Govindaraju, A. Lefohn, M. Houston, J. Owens, M. Segal, M. Papakipos, and I. Buck, "GPGPU: general-purpose computation on graphics hardware," in SC '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, (New York, NY, USA), p. 208, ACM, 2006.
18. H.-Y. Schive, C.-H. Chien, S.-K. Wong, Y.-C. Tsai, and T. Chiueh, "Graphic-card cluster for astrophysics (GraCCA) - performance tests," in Submitted to NewAstronomy, July 2007.
19. "IWLS 2005 Benchmarks." http://www.iwls.org/iwls2005/ benchmarks.html.
20. "NVIDIA Tesla GPU Computing Processor." http://www.nvidia.com/ object/ID_43499.html.
21. S. Parkes, P. Banerjee, and J. Patel, "A parallel algorithm for fault simulation based on proofs," in ICCD '95: Proceedings of the 1995 International Conference on Computer Design, (Washington, DC, USA), p. 616, IEEE Computer Society, 1995.
22. S. Patil and P. Banerjee, "Performance trade-offs in a parallel test generation/fault simulation environment," IEEE Transactions on Computer-Aided Design, pp. 1542-1558, Dec 1991.
23. "NVIDIA CUDA Introduction." http://www.beyond3d.com/content/ articles/12/1.
24. "NVIDIA CUDA Homepage." http://developer.nvidia.com/object/ cuda.html.