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Volumn , Issue , 2007, Pages 767-772

Impact of description language, abstraction layer, and value representation on simulation performance

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTER SIMULATION; MATHEMATICAL MODELS; VERIFICATION;

EID: 34548301460     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364688     Document Type: Conference Paper
Times cited : (14)

References (17)
  • 3
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    • Is this the merge of Verilog and VHDL
    • Boston
    • SystemVerilog: "Is this the merge of Verilog and VHDL": Proceedings of the SNUG Boston 2004.
    • (2004) Proceedings of the SNUG
    • SystemVerilog1
  • 4
    • 34548347639 scopus 로고
    • Synergy Between VHDL & Verilog
    • Users Meeting
    • Peet James: "Synergy Between VHDL & Verilog", Proceedings of VIUF Spring '95, Users Meeting
    • (1995) Proceedings of VIUF Spring
    • Peet James1
  • 5
    • 0029696610 scopus 로고    scopus 로고
    • Douglas Smith.: VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C, 33th DAC. 1996.
    • Douglas Smith.: "VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C", 33th DAC. 1996.
  • 7
    • 34548341297 scopus 로고    scopus 로고
    • Speed up Verilog Simulations by 10-100× without spending a penny
    • Rajesh Bawankule: "Speed up Verilog Simulations by 10-100× without spending a penny". Proceedings of the DVCon2003
    • Proceedings of the DVCon2003
    • Rajesh Bawankule1
  • 11
    • 34548353465 scopus 로고    scopus 로고
    • Evaluation of Sequential VHDL and C for System Description and Specification
    • Fall Meeting
    • Matthias Bauer, Wolfgang Ecker, Michael Gasteier, Manfred Glesner: "Evaluation of Sequential VHDL and C for System Description and Specification". Proceedings of the VUIF'96 Fall Meeting.
    • (1996) Proceedings of the VUIF
    • Bauer, M.1    Ecker, W.2    Michael Gasteier, M.G.3
  • 12
    • 34548347636 scopus 로고    scopus 로고
    • Evaluation of Ada'95 and VHDL for System Level Modeling
    • Spring Meeting
    • Wolfgang Ecker, Joerg Boettger. "Evaluation of Ada'95 and VHDL for System Level Modeling", Proceedings of the VIUF '97 Spring Meeting.
    • (1997) Proceedings of the VIUF
    • Ecker, W.1    Boettger, J.2
  • 13
    • 34548371313 scopus 로고    scopus 로고
    • Using SystemC for Hardware Design Comparison of results with VHDL, Cossap and CoCentric
    • Mario Steinert: "Using SystemC for Hardware Design Comparison of results with VHDL, Cossap and CoCentric, Proceedings of the ESNUG2002
    • Proceedings of the ESNUG2002
    • Mario Steinert1
  • 14
    • 34548371312 scopus 로고    scopus 로고
    • th DAC,
    • th DAC,
  • 17
    • 34548334135 scopus 로고    scopus 로고
    • SystemVerilog 2-State Simulation and Verification Advantages
    • Cliff Cumming, Lionel Benning: "SystemVerilog 2-State Simulation and Verification Advantages", Proceedings of Boston SNUG 2004
    • (2004) Proceedings of Boston SNUG
    • Cliff Cumming, L.B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.