A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 881-886

  Zambelli, C ^a   Indaco, M ^b   Fabiano, M ^b   Di Carlo, S ^b   Prinetto, P ^b   Olivo, P ^a   Bertozzi, D ^a  

^a UNIVERSITY OF FERRARA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CONTROLLERS; ECONOMIC AND SOCIAL EFFECTS; FLASH MEMORY; NAND CIRCUITS; RELIABILITY;

ALGORITHM SELECTION; ARCHITECTURE CONFIGURATION; CROSS-LAYER APPROACH; MULTI LEVEL CELL (MLC); OPTIMIZATION TECHNIQUES; PERFORMANCE AND RELIABILITIES; PERFORMANCE RELIABILITY; RELIABILITY-PERFORMANCE TRADE-OFFS;

MEMORY ARCHITECTURE;

EID: 84862059627     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176622     Document Type: Conference Paper

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