VLSI implementation of BCH error correction for multilevel cell NAND flash memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 5, 2010, Pages 843-847

  Choi, Hyojin ^a   Liu, Wei ^a   Sung, Wonyong ^b  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Bose Chaudhuri Hocquenghem (BCH) code; Memory error correction; NAND Flash memory; Solid state drive (SSD)

Indexed keywords

BIT-ERRORS; BOSE-CHAUDHURI-HOCQUENGHEM CODES; CHIP AREAS; CIRCUIT COMPLEXITY; CODE RATES; ERROR CORRECTING CODE; HIGH-THROUGHPUT; LOW POWER; MEMORY ERROR; MULTILEVEL CELL NAND; NAND FLASH; NAND FLASH MEMORY; POWER CONSUMPTION; RESOURCE SHARING; STORAGE SYSTEMS; TIME MULTIPLEXING; VLSI DESIGN; VLSI IMPLEMENTATION;

DRIVES; ERROR CORRECTION; INFORMATION THEORY; NAND CIRCUITS; PARALLEL ALGORITHMS; RANDOM ERRORS;

FLASH MEMORY;

EID: 77951879762     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2015666     Document Type: Article

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