High-voltage analog system for a mobile NAND flash

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 2, 2008, Pages 507-516

  Kang, Yong Hoon ^a   Kim, Jin Kook ^a   Hwang, Sang Won ^a   Kwak, Joon Young ^a   Park, Jun Yong ^a   Kim, Daeyong ^a   Kim, Chan Ho ^a   Park, Jong Yeol ^a   Jeong, Yong Taek ^a   Baek, Jong Nam ^a   Jeon, Su Chang ^a   Jang, Pyungmoon ^a   Lee, Sang Hoon ^a   Lee, You Sang ^a   Kim, Min Seok ^a   Lee, Jin Yub ^a   Choi, Yun Ho ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Analog circuit; Charge pump; High voltage analog circuit; High voltage charge pump; High voltage generator; High voltage regulator; Low ripple regulator; Low power NAND Flash; Low voltage NAND Flash; Low voltage oscillator; Mixed signal system on a chip

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; NAND CIRCUITS; OPTIMIZATION;

CHARGE PUMP; LOW SUPPLY VOLTAGE; LOW-VOLTAGE NAND FLASH;

ANALOG CIRCUITS;

EID: 38849152827     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.914327     Document Type: Article

References (17)

1. K. D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, J.-R. Kim, and H.-K. Lim, "A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme," in IEEE ISSCC 1995 Dig. Tech. Papers, San Francisco, CA, Feb. 1995, pp. 128-129.
2. T.-S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H. Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Lee, and H.-K. Lim, "A 3.3 V 128 Mb multi-level NAND Flash memory for mass storage applications," in IEEE ISSCC 1996 Dig. Tech. Papers, San Francisco, CA, Feb. 1996, pp. 32-33.
3. T. Cho, Y.-T. Lee, E. Kim, J. Lee, S. Choi, S. Lee, D.-H. Kim, W.-K. Han, Y.-H. Lim, J.-D. Lee, J.-D. Choi, and K.-D. Suh, "A 3.3 V 1 Gb multi-level NAND Flash memory with non-uniform threshold voltage distrution," in IEEE ISSCC 2001 Dig. Tech. Papers, San Francisco, CA, Feb. 2001, pp. 28-29.
4. 2 and-type 512 Mb Flash memory with 1.8 V power supply," in IEEE ISSCC 2001 Dig. Tech. Papers, San Francisco, CA, Feb. 2001, pp. 30-31.
5. R. Bez, E. E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to Flash memory," Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
6. C. Park, J. Seo, D. Seo, S. Kim, and B. Kim, "Cost-efficient memory architecture design of NAND Flash memory embedded systems," in Proc. Int. Conf. Computer Design, San Jose, CA, Oct. 2003, pp. 474-480.
7. E. J. Marinissen, B. Prince, D. Keitel-Schulz, and Y. Zorian, "Challenges in embedded memory design and test," in Proc. Design, Automation, and Test in Europe (DATE'05), Messe Munich, Germany, Mar. 2005, pp. 722-727.
8. J.-D. Lee, J.-H. Choi, D. Park, and K. Kim, "Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90-nm NAND Flash memory cells," in Proc. Int. Reliability Physics Symp., Dallas, TX, Mar. 2003, pp. 497-501.
9. J. Lee, H.-S. Im, D.-S. Byeon, K.-H. Lee, D.-H. Chae, K.-H. Lee, S. Hwang, S.-S. Lee, Y.-H. Lim, J.-D. Lee, J.-D. Choi, Y.-I. Seo, J.-S. Lee, and K.-D. Suh, "High-performance 1-Gb NAND Flash memory with 0.12-μm technology," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1502-1509, Nov. 2002.
10. K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung, and K.-D. Suh, "Floating-well charge pump circuits for sub-2.0 V single power supply Flash memories," in Symp. VLSI Circuits Dig. Tech. Papers, Kyoto, Japan, Jun. 1997, pp. 61-62.
11. J. F. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," IEEE J. Solid-State Circuits, vol. SSC-11, no. 2, pp. 374-378, Jun. 1976.
12. T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1231-1240, Aug. 1997.
13. G. Palumbo, D. Pappalardo, and M. Gaibotti, "Charge-pump circuits: power-consumption, optimization," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 49, no. 11, pp. 1535-1542, Nov. 2002.
14. J. Soldera, A. V. Boas, and A. Olmos, "A low ripple fully integrated charge pump regulator," in. Proc. 16th Symp. Integrated Circuits and Systems Design, Sep. 2003, pp. 177-180.
15. J.-Y. Lee, S.-E. Kim, S.-J. Song, J.-K. Kim, S. Kim, and H.-J. Yoo, "A regulated charge pump with small ripple voltage and fast start-up," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 425-432, Feb. 2006.
16. J. D. Choi, D. G. Lee, D. J. Kim, S. S. Cho, H. S. Kim, C. H. Shin, and S. T. Ahn, "A triple polysilicon stacked Flash memory cell with wordline self-boosting programming," in Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 1997, pp. 283-286.
17. D. A. Johns and D. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, ch. 16.