An adaptive-rate error correction scheme for NAND flash memory

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 53-58

  Chen, Te Hsuan ^a   Hsiao, Yu Ying ^a   Hsing, Yu Tsao ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

BCH code; Error correction; Flash memory; Memory fault tolerance; Memory management

Indexed keywords

BCH CODE; ECC SCHEME; ERROR CORRECTION CAPABILITY; ERROR-CORRECTION SCHEMES; HIGH NOISE LEVELS; MEMORY FAULT TOLERANCE; MEMORY MANAGEMENT; NAND FLASH MEMORY; STORAGE SPACES;

ERROR CORRECTION; FAULT TOLERANCE; QUALITY ASSURANCE;

FLASH MEMORY;

EID: 70350418733     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.24     Document Type: Conference Paper

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