Bounding worst-case data cache behavior by analytically deriving cache reference patterns

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn , Issue , 2005, Pages 148-157

  Ramaprasad, Harini ^a   Mueller, Frank ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISS EQUATIONS (CME); CACHE REFERENCE PATTERNS; SCHEDULABILITY; WORST CASE EXECUTION TIME (WCET);

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA ACQUISITION; PATTERN RECOGNITION; PROGRAM PROCESSORS; REAL TIME SYSTEMS;

DATA STORAGE EQUIPMENT;

EID: 24944584859     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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