Improved process flow for buried channel fabrication in silicon

Microsystem Technologies

Volumn 18, Issue 3, 2012, Pages 353-358

  Fekete, Z ^a,b   Pongracz A ^a   Furjes P ^a   Battistig, G ^a  

^a RESEARCH INSTITUTE FOR TECHNICAL PHYSICS AND MATERIALS SCIENCE   (Hungary)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED CHANNELS; CHIP SURFACES; DEEP REACTIVE ION ETCHING; FILLED TRENCH; FLUIDIC CHANNELS; IMPROVED PROCESS; MEMS TECHNOLOGY; MICRO FLUIDIC SYSTEM; MICRO-PROBES; PLANARITY; PROCESS FLOWS; PROTECTION METHODS; SI SUBSTRATES; SILICON SUBSTRATES; SURFACE PLANARITY;

FLUIDIC DEVICES; MICROCHANNELS; MICROFLUIDICS; SILICON WAFERS;

FABRICATION;

EID: 84861530786     PISSN: 09467076     EISSN: None     Source Type: Journal    
DOI: 10.1007/s00542-012-1430-3     Document Type: Article

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