VLSI on-chip power/ground network optimization considering decap leakage currents

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 735-738

  Fu, Jingjing ^a   Luo, Zuying ^a   Hong, Xianlong ^a   Cai, Yici ^a   Tan, Sheldon X D ^b   Pan, Zhu ^a  

^a TSINGHUA UNIVERSITY   (China)

^b University of California Riverside   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; VLSI CIRCUITS;

AREA-EFFICIENT; GATE OXIDE LAYERS; GATE-LEAKAGE CURRENT; LEAKAGE CURRENT MODELING; NETWORK OPTIMIZATION; ON-CHIP DECOUPLING CAPACITORS; POWER/GROUND NETWORK; SOURCE AND DRAINS;

LEAKAGE CURRENTS;

EID: 84861426001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121005     Document Type: Conference Paper

References (13)

1. The International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net/. 2002update.
2. T. K.arnik, S. Borkar, and V. De. Sub-90nm technologies-challenges and opportunities for CAD. In Proceeding of ICCAD2002, San Jose, 2002.11:203-207.
3. S. Mukhopadhyay, A. Raychowdhury, and K. Roy. Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling. In Proceeding of 40m DAC, Anaheim, 2003.6: 169-174.
4. D. W. Lee, W. Kwong, D. Blaauw, D. Sylvester. Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage, In Proceeding of 40th DAC, Anaheim, 2003.6: 175-180.
5. http://wvyw-device.eecs,berkeley.edu/~ptm/
6. I. A. Ferzli, F. N. Najm. Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. In Proceeding of ICCAD2003, San Jose, 2003.11: 770-777.
7. G Bai, S. Bobba, and I. N. Hajj. Simulation and optimization of the power distribution network in VLSI circuits. In Proceeding of ICCAD2000, San Jose, 2000.11: 481-486.
8. X. D. Tan and C. J. Shi. Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming. In Proceeding of 36,h ACM/IEEE DAC, New Orleans, 1999: 78-83.
9. X. H. Wu, X. L. Hong, Y. C. Cai, and et al. Area minimization of power distribution network using efficient nonlinear programming techniques. In Proceeding of 1CCAD2001, San Jose, 2001: 153-157.
10. S. Y. Zhao, K, K. Roy, C. K. Koh. Decoupling capacitance allocation for power supply noise suppression. In Proceeding of ISPD2001, Sonoma, 2001: 66-71.
11. H. H. Su, K. K. Roy, S. S. Sapatnekar, S. R. Nassif. An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. In Proceeding of ISPD2002, San Diego, 2002: 68-75.
12. J. J. Fu, Z. Y. Luo, X. L. Hong, Y. C. Cai, Sheldon. X. D. Tan, Z. Pan. A Fast Decoupling Capacitor Allocation Algorithm for Noise Reduction of Power Delivery Networks. In proceeding of ASP-DAC2004, Yokohama, 2004.1: 505-510.
13. K. Wang and M. M. Sadowska. On-chip Power Supply Network Optimization using Multigrid-based Technique. In Proceeding of. 40tb DAC, Anaheim, 2003.6: 113:118.