A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 505-510

  Fu, Jingjing ^a   Luo, Zuying ^a   Hong, Xianlong ^a   Cai, Yici ^a   Tan, Sheldon X D ^b   Pan, Zhu ^a  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); NONLINEAR PROGRAMMING; OPTIMIZATION; PROBLEM SOLVING; TIME DOMAIN ANALYSIS; VLSI CIRCUITS;

CLOCK NETWORKS; DECOUPLING CAPACITORS; ON-CHIP POWER DELIVERY;

CAPACITORS;

EID: 2442603407     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. H. H. Chen, D. D. Ling. "Power supply noise analysis methodology for deep-submicron VLSI chip design." Proc. 34th ACM/IEEE Design Automation Conf., pp. 638-643, 1997.
2. G. Bai, S. Bobba and I. N. Hajj, "Simulation and optimization of the power distribution network in VLSI circuits", Proc. IEEE/ACM International Conf. on Computer-Aided Design., pp. 481-486, 2000.
3. H.-H. Su, K. H. Gala, and S. S. Sapatnekar. "Fast analysis and optimization of power/ground networks." Proc. IEEE/ACM International Conf. on Computer-Aided Design., pp. 477-482, 2000.
4. X.-D. Tan and C.-J. Shi. "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming." Proc. 36th ACM/IEEE Design Automation Conf., pp. 78-83, 1999.
5. X.-H. Wu, X.-L. Hong, Y.-C. Cai, and et al. "Area minimization of power distribution network using efficient nonlinear programming techniques." Proc. IEEE/ACM International Conf. on Computer-Aided Design., pp. 153-157, 2001.
6. X.-D. Tan and C.-J. Shi. "Fast power-ground network optimization using equivalent circuit modeling," Proc. 38th ACM/IEEE Design Automation Conf., pp. 550-554, 2001.
7. S.-Y. Zhao, K.K. Roy, C.-K. Koh. "Decoupling capacitance allocation for power supply noise suppression." Proc. IEEE/ACM International Symp. on Physical Design, pp.66-71,2001.
8. H.-H. Su, K.K. Roy, S. S. Sapatnekar, S. R. Nassif. "An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts." Proc. IEEE/ACM International Symp. on Physical Design, pp.68-75, 2002.
9. T. Chen and C. C. Chen, "Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative method", Proc. ACM/IEEE Design Automation Conf., pp. 559-562, June, 2001.
10. A. Odabasioglu, M. Celik, and L. T. Pilleggi, "PRIMA: passive reduction-order interconnect macromodeling algorithm.," IEEE Trans. On Computer-Aided Design, vol. 17, no. 8, pp.645-654. 1998.
11. Y. Cao, Y.Lee, T.Chen and C.C. Chen, "HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery", Proc. ACM/IEEE Design Automation Conf., pp. 379-384, June, 2002.
12. D. Stark and M. Horowitz, "Techniques for calculating currents and voltages in VLSI power supply networks," IEEE Trans. on Computer-Aided Design, vol. 9, no. 2, pp. 126-132, February 1990.
13. A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu and D. Bearden, "Design and analysis of power distribution networks in power PC microprocessors", Proc. ACM/IEEE Design Automation Conf., pp. 738-743, June, 1998.
14. Y.-M. Lee, C.-P. Chen. "Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method." Proc. IEEE/ACM International Conf. on Computer-Aided Design., pp. 75-80, 2001.
15. J. N. Kozhaya, S. R. Nassif, and F.N. Najm. "A multigrid-like technique for power grid analysis. IEEE Trans. Computer-Aided Design, vol. 21, no.10, pp. 1148-1160, Oct. 2002.
16. M. Zhao, R. V. Panda, S. S. Sapatnekar and D. Blaauw, "Hierarchical analysis of power distribution networks", IEEE Trans. Computer-Aided Design, vol. 9, no. 2, pp. 159-168, Apr. 1990.
17. L.O. Chua and P.M. Lin, Computer-Aided Analysis of Electronic Circuits, Englewood Cliffs: Prentice-Hall, Inc. 1975.
18. K. Wang and M. Marek-Sadowask, "On-chip power supply network optimization using multigrid-based technique", Proc. ACM/IEEE Design Automation Conf., pp. 113-118, June, 2003.