On the use of nanoelectronic logic cells based on metallic Single Electron Transistors

2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012

Volumn , Issue , 2012, Pages 157-160

  Bounouar, Mohamed Amine ^a,b   Beaumont, Arnaud ^b   Calmon, Francis ^b   Drouin, Dominique ^a  

^a UNIVERSITÉ DE SHERBROOKE   (Canada)

^b UNIVERSITÉ DE LYON   (France)

Author keywords

Hybrid SET CMOS architectures; Low power consumption; Metallic Single Electron Transistor (SET); Nanoelectronic logic cells; Room Temperature Operation

Indexed keywords

CMOS TECHNOLOGY; COMPUTING ARCHITECTURE; LOGIC CELLS; LOW VOLTAGE OPERATION; LOW-POWER CONSUMPTION; ROOM TEMPERATURE; ROOM-TEMPERATURE OPERATION;

CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; LOGIC CIRCUITS; LOGIC DEVICES; NANOELECTRONICS;

SINGLE ELECTRON TRANSISTORS;

EID: 84861217548     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ULIS.2012.6193381     Document Type: Conference Paper

References (17)

1. Greenpeace International, "How dirty is your data? A Look at the Energy Choices That Power Cloud Computing,"http://www.greenpeace.org/ international/Global/international/publications/climate/2011/Cool%20IT/ dirty-data-report-greenpeace.pdf.
2. R. Hartenstein "Aiming at the Natural Equilibrium of Planet Earth Requires to Reinvent Computing," Keynote ISCAS conference, 2011.
3. ITRS 2010 Edition, Process Integration, Devices & Structures, http://www.itrs.net.
4. J. R. Tucker, "Complementary digital logic based on the "Coulomb blockade," J. Appl. Phys., vol. 72, no. 9, pp. 4399-4413, Nov. 1992.
5. C. Zhu, et al. "Towards an ultra-low-power architecture using single-electron tunneling transistors," in Proc. IEEE - DAC, June. 2007.
6. C. Gerousis, S. M. Goodnick, W. Porod, "Nanoelectronic Single-electron Transistor Circuits and Architectures," International Journal of Circuit Theory and Applications., vol. 32, pp. 323-538, 2004.
7. K. Likharev, "Single-Electron Devices and Their Applications," Proc. IEEE, Vol. 87, No. 4, pp. 606-632, 1999.
8. A. Beaumont, M. Guilmain, C. Dubuc, J. Beauvais, D. Drouin, "MARSSEA, a simulator for high temperature single electron devices", to be published.
9. M. A. Bounouar, F. Calmon, A. Beaumont, M. Guilmain, W. Xuan, S. Ecoffey, D. Drouin, "Single Electron Transistor Analytical Model for Hybrid Circuit Design," proc. of IEEE - NEWCAS conference, pp. 506- 509, 2011.
10. S. Mahapatra et al. "Analytical Modeling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design," IEEE Trans. Elec. Dev., vol. 51, no. 11, pp. 1772-1782, 2004.
11. C. Dubuc, A. Beaumont, J. Beauvais, D. Drouin, "Current conduction models in high temperature single electron transistor," Solid State Electronics 53, pp. 478-482 (2009).
12. C. Dubuc, "Design and fabrication of single-electron transistors with wide operating temperature range," PhD thesis, Univ. of Sherbrooke, 2008.
13. S. Mahapatra, A. Ionescu, K. Banerjee and M. Declercq, "Modelling and analysis of power dissipation in single electron logic," Proc. of IEEE IEDM conference, pp. 323-326, 2002.
14. I. J. Chang, J. J. Kim, S. P. Park, K. Roy, "A 32 Kb 10T Subthreshold SRAM Array with Bit-Interlaving and Differential Read Scheme in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 388-389, Feb. 2008.
15. B. H. Calhoun and A. P. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, July 2006.
16. A. Beaumont, C. Dubuc, J. Beauvais, D. Drouin, "Room temperature single electron transistor with on-state current enhanced by the surface gate," IEEE Electron Device Letters 30, pp.766-768 (2009).
17. C. Dubuc, J. Beauvais, D. Drouin, "A nanodamascene process for advanced single-electron transistor fabrication," IEEE Trans. Nanotechnol., vol.7, no. 1, pp. 68-73, Jan. 2008.