Single Electron Transistor analytical model for hybrid circuit design

2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

Volumn , Issue , 2011, Pages 506-509

  Bounouar, M A ^a,b   Calmon, F ^b   Beaumont, A ^b   Guilmain, M ^a   Xuan, W ^b   Ecoffey, S ^a   Drouin, D ^a  

^a UNIVERSITÉ DE SHERBROOKE   (Canada)

^b UNIVERSITÉ DE LYON   (France)

Author keywords

Coulomb blockade; Hybrid SET CMOS circuit design; SET modeling; Single electron transistor (SET)

Indexed keywords

ANALYTICAL MODEL; CIRCUIT DESIGNS; COMPACT MODEL; COMPACT SETS; HYBRID CIRCUIT; LOGIC CIRCUIT DESIGN; PHYSICAL CHARACTERISTICS; ROOM TEMPERATURE; SET MODELING; SINGLE ELECTRON; STEADY STATE; UNIVERSAL LOGIC GATE; VERILOG-A;

CAPACITANCE MEASUREMENT; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK ANALYSIS; ELECTRON TRAPS; EQUATIONS OF STATE; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS; MODELS; THERMIONIC EMISSION; TRANSIENTS; TUNNEL JUNCTIONS;

SINGLE ELECTRON TRANSISTORS;

EID: 80052552533     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2011.5981330     Document Type: Conference Paper

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