High density metal-metal interconnect bonding for 3-d integration

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 2, Issue 1, 2012, Pages 71-78

  Lannon, John M ^a   Gregory, Chris ^a   Lueck, Matthew ^a   Reed, Jason D ^a   Huffman, Charles A ^a   Temple, Dorota ^a  

^a RTI INTERNATIONAL   (United States)

Author keywords

3 D integration; 3 D interconnect; Cu Cu interconnects; Cu Sn Cu interconnects; high density interconnect bonding; solid liquid diffusion bonding; thermo compression bonding

Indexed keywords

3-D INTEGRATION; 3-D INTERCONNECT; HIGH DENSITY INTERCONNECTS; SOLID-LIQUID; THERMO COMPRESSION BONDING;

INTEGRATION; THREE DIMENSIONAL;

METALS;

EID: 84859083362     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2175922     Document Type: Review

References (13)

1. P. Marchal, B. Bougard, G. Katti, M. Stucchi, W. Dehaene, A. Papanikolaou, D. Verkest, B. Swinnen, and E. Beyne, "3-D technology assessment: Path finding the technology/design sweet spot," Proc. IEEE, vol. 97, no. 1, pp. 96-107, Jan. 2009.
2. K. Snoeckx, E. Beyne, and B. Swinnen, "3D-stacked IC integration," Solid State Technol., pp. 53-55, May 2007.
3. P. Benkart, A. Munding, A. Kaiser, E. Kohn, A. Heitmann, H. Huebner, and U. Ramacher, "3-D integration scheme with a thermal budget below 300 °C," Sensors Actuators, vol. 139, nos. 1-2, pp. 350-355, Sep. 2007. (Pubitemid 47314217)
4. K. Tanida, M. Umemoto, T. Morifuji, R. Kajiwara, T. Ando, Y. Tomita, N. Tanaka, and K. Takahashi, "Au bump interconnection in 20 μm pitch on 3D chip stacking technology," Jpn. J. Appl. Phys., vol. 42, no. 10, pp. 6390-6395, 2003.
5. P. R. Morrow, C.-M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "3-D wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/Low-k CMOS technology," IEEE Electron Devi. Lett., vol. 27, no. 5, pp. 335-337, May 2006.
6. H. Huebner, S. Penka, B. Barchmann, M. Eigner, W. Gruber, M. Nobis, S. Janka, G. Kristen, and M. Schneegans, "Microcontacts with sub-30 μm pitch for 3D chip-on-chip integration," Microelectron. Eng., vol. 83, nos. 11-12, pp. 2155-2162, 2006. (Pubitemid 44792793)
7. K. Tanida, M. Umemoto, N. Tanaka, Y. Tomita, and K. Takahashi, "Micro Cu bump interconnection on 3D chip stacking technology," Jpn. J. Appl. Phys., vol. 43, no. 4, pp. 2264-2270, 2004.
8. P. Benkart, A. Kaiser, A. Mundling, M. Bschorr, H.-J. Pfleiderer, E. Kohn, A. Heittmann, H. Huebner, and U. Ramacher, "3D chip stack technology using through-chip interconnects," IEEE Desi. Test Comput., vol. 22, no. 6, pp. 512-518, Nov./Dec. 2005. (Pubitemid 41715958)
9. A. Huffman, M. Lueck, C. Bower, and D. Temple, "Effects of assembly process parameters on the structure and thermal stability of Sn-capped Cu bump bonds," in Proc. 57th Electron. Compon. Technol. Conf., Reno, NV, 2007, pp. 1589-1596. (Pubitemid 47577240)
10. N. Koopman and S. Nangalia, "Fluxless flip chip solder joining," in Proc. NEPCON West, Anaheim, CA, 1995, pp. 919-931.
11. J. Lannon, C. Gregory, A. Huffman, M. Lueck, and D. Temple, "High density Cu-Cu interconnect bonding for 3D integration," in Proc. 59th Electron. Comp. Technol. Conf., May 2009, pp. 355-359.
12. K. Tanida, M. Umemoto, Y. Tomita, M. Tago, Y. Nemoto, T. Ando, and K. Takahashi, "Ultrahigh density 3D chip stacking technology," in Proc. 43rd Electron. Comp. Technol. Conf., 2003, pp. 1084-1089.
13. K. Chen, A. Fan, C. Tan, and R. Reif, "Bonding parameters of blanket copper wafer bonding," J. Electron. Mater., vol. 35, no. 2, pp. 230-234, 2006. (Pubitemid 43384535)