A register-file approach for row buffer caches in die-stacked DRAMs

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 351-361

  Loh, Gabriel H ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASE LAYERS; BUFFER CACHES; COMPILER DESIGN; DE-ALLOCATION; DRAM TECHNOLOGY; INTERFACE LOGIC; MEMORY ACCESS; MEMORY CELL; MEMORY STACK; MULTIPLE LAYERS; PERFORMANCE BENEFITS; PERIPHERAL CIRCUITRY; REGISTER ALLOCATION; SENSE AMP; TEST STRUCTURE; TIMING CONSTRAINTS;

DYNAMIC RANDOM ACCESS STORAGE; TIMING CIRCUITS;

CACHE MEMORY;

EID: 84858775807     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155662     Document Type: Conference Paper

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