A (64,45) triple error correction code for memory applications

IEEE Transactions on Device and Materials Reliability

Volumn 12, Issue 1, 2012, Pages 101-106

  Reviriego, Pedro ^a   Flanagan, Mark ^b   Maestro, Juan Antonio ^a  

^a UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

^b UNIVERSITY COLLEGE DUBLIN   (Ireland)

Author keywords

Difference set codes; error correction codes (ECCs); majority logic decoding; memory

Indexed keywords

DATA CORRUPTION; DECODABLE CODES; DIFFERENCE-SET CODES; ERROR CORRECTION CAPABILITY; ERROR CORRECTION CODES; ERROR CORRECTION CODES (ECCS); LOW LATENCY; LOW-COMPLEXITY; MAJORITY LOGIC DECODING; MEMORY APPLICATIONS; MEMORY DESIGN; MEMORY PROTECTION; MODERATE COMPLEXITY; SOFT ERROR; WORD LENGTH;

DATA STORAGE EQUIPMENT; DECODING; MAJORITY LOGIC; PROGRAM PROCESSORS;

ERROR CORRECTION;

EID: 84858141999     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2011.2169413     Document Type: Article

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