Improved decoding algorithm for high reliable Reed Muller coding

Proceedings - 20th Anniversary IEEE International SOC Conference

Volumn , Issue , 2007, Pages 95-98

  Argyrides, Costas ^a   Pradhan, Dhiraj K ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

PROGRAMMING THEORY;

ON CHIPS; REED MULLER CODING;

DECODING;

EID: 51049099146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2007.4545435     Document Type: Conference Paper

References (20)

1. A.M. Saleh, J.J. Serrano, and J.H Patel, "Reliability of Scrubbing Recovery Techniques for Memory Systems," IEEE Trans. on Reliability, Vol. 39, NO. 1, pp. 114-122, 1990.
2. C. Argyrides, H.R. Zarandi, D.K. Pradhan, "Multiple Upsets Tolerance in SRAM Memory," ISCAS07, New Orleans, USA, 27-30 May, 2007.
3. Costas Argyrides, Dhiraj K. Pradhan "Highly Reliable Power Aware Memory Design". IOLTS 2007, Page(s) 189-190, July 2007
4. C.S Wallace, "A Suggestion for a Fast Multiplier" in IEEE Trans. On Electronic Computer, Volume EC-13, Issue 1, Page(s):14 17 Feb. 1964
5. D. Bertozzi et al. "Error control schemes for on-chip communication links: the energy-reliability tradeoff" in IEEE Trans. on DAC, Vol. 24, No. 6, June 2005.
6. D.K Prahdan, S.M. Reddy "Error-Control Techniques for Logic Processors", in IEEE Trans. on Comp. Vol C-21, No 12, Dec 1972
7. D.Rossi, C. Metra "Error correcting strategy for high speed and density reliable flash memories" in IEEE J. Electronic Testing, Theory and applications. Vol. 19, No. 5. pp 511-521 Nov 2003
8. I. Reed, "A class of multiple-error-correcting codes and the decoding scheme" in IEEE Trans. on Information Theory, Vol. 4, Issue 4, Page(s):38-49, Sep 1954
9. Jr. AssmusE.F. and Key, J.D. "Designs and their Codes". Press Syndicate of the University of Cambridge, Cambridge 1992.
10. K. Itoh " Trends in megabit DRAM circuit design", in IEEE J. Solid State Circuits, Vol 25, pp 778-789, June 1990.
11. K. Itoh et al. "Trends in low-power RAM circuit technologies" , in Proc IEEE ., Vol. 83, pp524-543, April 1995
12. K. Kimura et al, "Power reduction in megabit DRAM's, in IEEE Journal of Solid State Circuits, Vol SSC-21, pp. 381-389, June 1986.
13. M. Margala and N.G. Durdle, "Noncomplementaty BiCMOS logic and CMOS logic styles for low-voltage operation- A comprehensive study". In IEEE J. Solid State Circuits, vol 33, pp1580-1585, Oct 1998.
14. th IEEE VLSI Test Symposium. p. 86, 1999
15. P. Hazucha et al. "Measurements and Analysis of SER-Tolerant Latch in a 90-nm Dual-VT CMOS Process" in IEEE Journal of Solid-State Circ., Vol. 39, No. 9, Sept 2004
16. S. Mitra et al., "Robust System Design with Built-In Soft-Error Resilience" , in IEEE computer society, Vol. 38, No. 2 pp. 43-52 , Feb. 2005
17. S. Bhattacharjee and D. K. Pradhan, "LPRAM A novel Low-Power High-Performance RAM design with testability and Scalability" in IEEE Trans. on Computers , Vol. 23, No. 5, May 2004.
18. S. Roman, "Coding and information Theory", Graduate Texts in Mathematics, 1992.
19. T. Kinichiroh et al., "New Decoding Algorithm for Reed-Muller Codes", in IEEE Trans. on Infornation. Theory, Vol. IT-28, No5 Sept 1982
20. T.R.N. Rao and E. Fujiwara, "Error-Control Coding for Computer Systems", Published by Prentice Hall, New Jersey, 1989