Fault secure encoder and decoder for nanoMemory applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 4, 2009, Pages 473-486

  Naeimi, Helia ^a   Dehon, André ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

Decoder; Encoder; Fault tolerant; Memory; Nanotechnology

Indexed keywords

ARTIFICIAL INTELLIGENCE; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; INFORMATION THEORY; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; NANOWIRES; SWITCHING CIRCUITS; SYSTEMS ENGINEERING;

AREA OVERHEADS; DECODER; DEFECT RATES; DESIGN FAULTS; ENCODER; ERROR-CORRECTING CODES; EUCLIDEAN GEOMETRIES; FAILURE RATES; FAULT RATES; FAULT SECURE; FAULT TOLERANT; LDPC CODES; LOW DENSITY PARITY CHECKS; MEMORY; MEMORY BLOCKS; MEMORY CELLS; MEMORY DENSITIES; MEMORY DESIGNS; MEMORY SYSTEMS; NEW APPROACHES; NEW CLASS; SOFT ERROR RATES; SOFT ERRORS; SYSTEM FAILURES; TRANSIENT ERRORS;

DECODING;

EID: 62949103821     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2009217     Document Type: Article

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