A soft-error tolerant Content-addressable Memory (CAM) using an error-correcting-match scheme

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 301-304

  Pagiamtzis, Kostas ^a   Azizi, Navid ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISSIPATION; ERROR CORRECTION; INTEGRATED CIRCUIT MANUFACTURE; STATIC RANDOM ACCESS STORAGE;

CONTENT ADDRESSABLE MEMORY (CAM); ERROR CORRECTING CODES (ECC); SOFT ERROR RATE;

ASSOCIATIVE STORAGE;

EID: 39049144737     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320887     Document Type: Conference Paper

References (9)

1. K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Match 2006.
2. H. J. Chao, ''Next generation routers," Proc. IEEE, vol. 90, no. 9, pp. 1518-1558, September 2002.
3. R. C. Baumann, "Soft errors in advanced semiconductor devices - Part I: Three radiation sources," IEEE Trans. Device Mat. Rel., vol. 1, no. 1, pp. 17-22, March 2001.
4. H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, et al., "A cost-efficient high-performance dynamic TCAM with pipelined hierarchical search and shift redundancy architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245-253, January 2005.
5. H. Noda, K. Dosaka, F. Morishita, K. Arimoto, et al., "A soft-error immune maintenance-free TCAM architecture with associated embedded DRAM," in IEEE Custom Integrated Circuits Conf., September 2005, pp. 451-454.
6. I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary contents addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 155-158, January 2003.
7. S. B. Wicker, Error Control Systems for Digital Communication and Storage. New Jersey: Prentice Hall, 1995.
8. S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, "On-chip error correcting techniques for new-generation flash memories," Proc. IEEE, vol. 91, no. 4, pp. 602-616, April 2003.
9. P.-F. Lin and J. B. Kuo, "A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1307-1317, October 2002.