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Volumn , Issue , 2008, Pages 37-42

New linear SEC-DED codes with reduced triple error miscorrection probability

Author keywords

[No Author keywords available]

Indexed keywords

ADMINISTRATIVE DATA PROCESSING; CODES (STANDARDS); CONTROL THEORY; ERROR CORRECTION; ERRORS; PROBABILITY;

EID: 52049098657     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.27     Document Type: Conference Paper
Times cited : (41)

References (15)
  • 1
    • 35448956611 scopus 로고
    • A class of systematic codes for non-independent errors
    • December
    • N. M. Abramson. A class of systematic codes for non-independent errors. IEEE Transactions on Information Theory, 5(4):150-157, December 1959.
    • (1959) IEEE Transactions on Information Theory , vol.5 , Issue.4 , pp. 150-157
    • Abramson, N.M.1
  • 2
    • 0037592480 scopus 로고    scopus 로고
    • Evolution strategies - A comprehensive introduction
    • Mar
    • H.-G. Beyer and H.-P. Schwefel. Evolution strategies - A comprehensive introduction. Natural Computing, 1(1):3-52, Mar. 2002.
    • (2002) Natural Computing , vol.1 , Issue.1 , pp. 3-52
    • Beyer, H.-G.1    Schwefel, H.-P.2
  • 4
    • 0021392066 scopus 로고
    • Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the Art Review
    • C. Chen and M. Hsiao. Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the Art Review. IBM Journal of Research and Development, 28:124-134, 1984.
    • (1984) IBM Journal of Research and Development , vol.28 , pp. 124-134
    • Chen, C.1    Hsiao, M.2
  • 5
    • 37549069366 scopus 로고    scopus 로고
    • Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
    • 6-10 May
    • A. Dutta and N. Touba. Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. In VLSI Test Symposium, 2007. 25th IEEE, pages 349-354, 6-10 May 2007.
    • (2007) VLSI Test Symposium, 2007. 25th IEEE , pp. 349-354
    • Dutta, A.1    Touba, N.2
  • 6
    • 0025454898 scopus 로고
    • Error-control coding in computers
    • E. Fujiwara and D. Pradhan. Error-control coding in computers. Computer, 23(7):63-72, 1990.
    • (1990) Computer , vol.23 , Issue.7 , pp. 63-72
    • Fujiwara, E.1    Pradhan, D.2
  • 8
    • 84943817322 scopus 로고
    • Error Detecting and Correcting Codes
    • Apr
    • R. W. Hamming. Error Detecting and Correcting Codes. The Bell System Technical Journal, 29(2):147-16, Apr. 1950.
    • (1950) The Bell System Technical Journal , vol.29 , Issue.2 , pp. 147-216
    • Hamming, R.W.1
  • 11
    • 0016508156 scopus 로고
    • Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement
    • May
    • M. Y. Hsiao and D. C. Bossen. Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement. IEEE Transactions on Computers, 24(5):512-516, May 1975.
    • (1975) IEEE Transactions on Computers , vol.24 , Issue.5 , pp. 512-516
    • Hsiao, M.Y.1    Bossen, D.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.