Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 935-945

  Bajura, Michael A ^a,b   Boulghassoul, Younes ^a,b   Naseer, Riaz ^a,b   DasGupta, Sandeepan ^a,c   Witulski, Arthur F ^a,c   Sondeen, Jeff ^b   Stansberry, Scott D ^b   Draper, Jeffrey ^a,b   Massengill, Lloyd W ^a,c   Damoulakis, John N ^b  

^a IEEE

^b Information Sciences Institute ^*  (United States)

^c VANDERBILT UNIVERSITY   (United States)

Author keywords

Error correction coding; Memory fault tolerance; Radiation effects

Indexed keywords

BIT ERROR RATE; DATA STORAGE EQUIPMENT; ERROR CORRECTION; MATHEMATICAL MODELS; RADIATION EFFECTS;

ERROR-CORRECTING CODES; MEMORY CELLS; MEMORY FAULT TOLERANCE;

STATIC RANDOM ACCESS STORAGE;

EID: 34548090143     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.892119     Document Type: Conference Paper

References (38)

1. C. W. Slayman, "Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 397-404, Sep. 2005.
2. R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 305-316, Sep. 2005.
3. N. Deracobian, V. Vardanian, and Y. Zorian, "Embedded memory reliability: The SER challenge," in Records IEEE Int. Workshop on Memory Techno!, Design and Testing, Aug. 2004, pp. 104-110.
4. P. E. Dodd, "Physics-based simulation of single-event effects," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 343-357, Sep. 2005.
5. J. Baggio, V. Ferlet-Cavrois, H. Duarte, and O. Flament, "Analysis of proton/neturon. SEU sensitivity of commercial SRAMs-Application, to the terrestrial environment test method," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3420-3426, Dec. 2004.
6. M. Spica and T. Mak, "Do we need anything more than single bit error correction (ECC)?," in Records IEEE Int. Workshop on Memory Technol., Design and Testing, Aug. 2004, pp. 111-116.
7. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multi-bit soft error events in advanced SRAMs," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 2003, pp. 21.4.1-21.4.4.
8. D. Radaelli, H. Puchner, S. Wong, and S. Daniel, "Investigation of multi-bit upsets in a 150 nm technology SRAM device," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2433-2437, Dec. 2005.
9. P. J. Meaney, S. B. Swaney, P. N. Sanda, and L. Spainhower, "IBM z990 soft error detection and recovery," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 419-427, Sep. 2005.
10. P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583-602, Jun. 2003.
11. J. Benedetto, P. Eaton, K. Avery, M. Gadlage, T. Turflinger, P. Dodd, and G. Vizkelethyd, "Heavy-ion-induced digital single-event transients in deep submicron processes," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3480-3485, Dec. 2004.
12. Honeywell SRAM, MRAM, and FIFO Rad Hard Memories. Honeywell, Solid State Electronics Ctr., Plymouth, MN, Aug. 2006 [Online], Available: http://www.ssec.honeywell.com/aerospace/radhard/memory.html
13. Aeroflex RadHard-by-Design SRAMs. Aeroflex, Colorado Springs, CO, Aug. 2006 [Online], Available: http://ams.aeroflex.com/Product-Pages/RH_4Msram.cfm
14. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
15. J. D. Black, A. L. Sternberg, M. L. Alles, A. F. Witulski, B. L. Bhuva, L. W. Massengill, J. M. Benedetto, M. P. Baze, J. L. Wert, and M. G. Hubert, "HBD layout isolation techniques for multiple node charge collection mitigation,"IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2536-2541, Dec. 2005.
16. A. M. Saleh, J. J. Serrano, and J. H. Patel, "Reliability of scrubbing recovery-techniques for memory systems," IEEE Trans. Reliab., vol. 39, no. 1, pp. 114-122, Apr. 1990.
17. Cosmic ray effects on micro-electronics (CREME96). U.S. Naval Research Lab., Washington, DC, Sep. 2006 [Online]. Available: https://creme96.nrl.navy. mil
18. Intel Server/Workstation Chipsets Comparison Chart. Intel, Santa Clara, CA, Aug. 2006 [Online]. Available: http://www.intel.com/design/chipsets/ linecard/linecard_srvrwrkstn.pdf
19. J. L. Shin, B. Petrick, M. Singh, and A. S. Leon, "Design and implementation of an embedded 5.12-kb level-2 cache subsystem," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1815-1820, Sep. 2005.
20. S. Mukherjee, J. Emmer, T. Fossum, and S. K. Reindhardt, "Cache scrubbing in microprocessors: Myth or necessity?," in Proc. 10th IEEE Pacific Rim Int. Symp. Dependable Comput., 2004, pp. 37-42.
21. C. L. Chen and M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: A state-of-the-art review," IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, Mar. 1984.
22. M. Y. Hsiao, "A class of optimal minimum odd-weight-column SEC-DED codes," IBM J. Res. Develop., vol. 14, no. 4, pp. 395-401, Jul. 1970.
23. S. Lin and D. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice Hall, 2004.
24. J. A. Zoutendyk, L. D. Edmonds, and L. S. Smith, "Characterization of multiple-bit errors from single-ion tracks in integrated circuits," IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2267-2274, Dec. 1989.
25. R. Koga, S. D. Pingerton, S. C. Moss, D. C. Mayer, S. LaLumondiere, S. J. Hansel, K. B. Crawford, and W. R. Crain, "Observation of single event upsets in analog microcircuits," IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1838-1844, Dec. 1993.
26. K. M. Warren, R. A. Weller, M. H. Mendenhall, R. A. Reed, D. R. Ball, C. L. Howe, B. D. Olson, M. L. Alles, L. W. Massengill, R. D. Schrimpf, N. F. Haddad, S. E. Doyle, D. McMorrow, J. S. Melinger, and W. T. Lotshaw, "The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2125-2131, Dec. 2005.
27. D. Y. Lam, J. Lan, L. McMurchie, and C. Sechen, " SEE-hardened-by-design area-efficient SRAMs," in Proc. IEEE Aerospace Conf., Mar. 2005, pp. 1-7.
28. O. A. Amusan, A. F. Witulski, L. W. Massengill, B. L. Bhuva, P. R. Fleming, M. L. Alles, A. L. Sternberg, J. D. Black, and R. D. Schrimpf, "Charge collection and charge sharing in a 130 nm CMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3253-3258, Dec. 2006.
29. J. Barth, "Modeling space radiation environments," presented at the IEEE Nuclear and Space Radiation Effects Conf. Short Course, Snowmass Village, CO, 1997.
30. t 9-mb third-level on-die cache for the 1.7-GHz Itanium 2 processor," IEEE J. Solid-State. Circuits, vol. 40, no. 1, pp. 195-203, Jan. 2005.
31. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, "Reliability tradeoffs in design of cache memories," presented at the 1st Workshop on Architectural Reliability (held in conjunction with 38th Int. Symp. Microarchitecture, MICRO-38), Barcelona, Spain, Nov. 2005 [Online]. Available: http://www.cs.binghamton.edu/oguz/war2005/index.html
32. M. Horowitz, E. Alon, D. Potil, S. Naffziger, R. Kumar, and K. Bernstein, "Scaling, power, and the future of CMOS," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 2005, pp. 9-15.
33. N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," IEEE Computer; vol. 36, no. 12, pp. 68-75, Dec. 2003.
34. N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and microarchitectural techniques for teducing cache leakage power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 167-184, Feb. 2004.
35. t transistors," in Proc. 7th IEEE Int. Symp. Quality Electronic Design (ISQED'06), Mar. 2006, pp. 27-29.
36. B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, Jul. 2006.
37. O. Thomas, M. Belleville, F. Jacquet, and P. Flatresse, "Impact of CMOS technology scaling on SRAM standby leakage reduction techniques," in Proc. IEEE Int. Conf. Integrated Circuit Design and Technol. (ICICDT), 2006, pp. 1-5.
38. V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M. J. Irwin, "Soft errors issues in low-power caches," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 10, pp. 1157-1166, Oct. 2005.